axi_tdl 0.1.7 → 0.1.8
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +5 -5
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +5 -5
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +4 -4
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi_tdl.rb +2 -2
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +2 -3
- data/lib/tdl/auto_script/import_hdl.rb +4 -4
- data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
- data/lib/tdl/class_hdl/hdl_generate.rb +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -153
- data/lib/tdl/examples/8_top_module/test_top.sv +26 -7
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +7 -26
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +1 -1
- metadata +2 -2
checksums.yaml
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@@ -1,7 +1,7 @@
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---
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metadata.gz:
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data.tar.gz:
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metadata.gz: 9882619ceed9e5f4f9f938e9a7fe5df14f23ab5c4bf477e95e4e0b95f5089d71
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data.tar.gz: 42251130e7992348d2a5a46485e6c477e1aebf6e23b0ae17fc2c85853385e046
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metadata.gz: fb193b722dd553b3e8b831fc9defa2205e44e985182d9b35dde6a5b54be296b97cdd02b52f870c65cbd9aab9b23a12e7e26b853235c6671ece805071a3516201
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data.tar.gz: 1b8ebba865c374baa1c3e8f07c207910e55cacfddd40dcc15637f409c168791dcc07b0c85f7530a9bd11e4feb252127196b64e6ab30ca70db0d6ba8e00d552fe
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@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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***********************************************/
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`timescale 1ns/1ps
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@@ -56,7 +56,7 @@ logic stream_en;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM))
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1624 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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@@ -94,13 +94,13 @@ independent_clock_fifo #(
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axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
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/* output */.stream_en (stream_en ),
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/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1624 )
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);
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vcs_axi4_comptable #(
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.ORIGIN ("master_wr_aux_no_resp" ),
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.TO ("master_wr" )
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)
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/* input */.origin (
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)vcs_axi4_comptable_axi_wr_aux_R675_axi_wr_inst(
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/* input */.origin (axi_wr_vcs_cp_R1624 ),
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/* output */.to (axi_wr )
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);
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axis_valve_with_pipe #(
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@@ -31,8 +31,8 @@ TdlBuild.data_inf_partition(__dir__) do
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logic - 'tail_len'
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logic - 'one_long_stream'
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logic - 'fifo_wr'
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-
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logic - 'fifo_full'
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logic - 'fifo_empty'
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always_comb do
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CASE ps.C do
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@@ -267,8 +267,12 @@ TdlBuild.data_inf_partition(__dir__) do
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end
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### Track
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debugLogic[10] - 'st5_cnt'
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debugLogic - 'track_st5'
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# debugLogic[10] - 'st5_cnt'
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# debugLogic - 'track_st5'
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logic[10] - 'st5_cnt'
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logic - 'track_st5'
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always_ff(posedge.clock,negedge.rst_n) do
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IF ~rst_n do
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st5_cnt <= 0.A
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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***********************************************/
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`timescale 1ns/1ps
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logic tail_len;
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logic one_long_stream;
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logic fifo_wr;
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logic fifo_full;
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logic fifo_empty;
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logic [IDSIZE+4-1:0] curr_id ;
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logic [LSIZE-1:0] curr_length ;
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logic [(data_in.DSIZE - IDSIZE)-LSIZE-1:0] curr_addr ;
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logic [LSIZE-1:0] wr_length ;
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-
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(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic [9:0] st5_cnt ;
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(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic track_st5;
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logic [10-1:0] st5_cnt ;
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logic track_st5;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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***********************************************/
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`timescale 1ns/1ps
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM))
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1219 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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/* output */.full (fifo_full )
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axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
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/* output */.stream_en (stream_en
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/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
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/* output */.stream_en (stream_en ),
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/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1219 )
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);
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vcs_axi4_comptable #(
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.ORIGIN ("master_wr_aux_no_resp" ),
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.TO ("master_wr" )
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)
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/* input */.origin (
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/* output */.to (axi_wr
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)vcs_axi4_comptable_axi_wr_aux_R827_axi_wr_inst(
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/* input */.origin (axi_wr_vcs_cp_R1219 ),
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/* output */.to (axi_wr )
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);
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axis_valve_with_pipe #(
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.MODE ("OUT" )
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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***********************************************/
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`timescale 1ns/1ps
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//-------- CLOCKs Total 3 ----------------------
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//--->> CheckClock <<----------------
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logic
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integer
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ClockSameDomain
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logic cc_done_6,cc_same_6;
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integer cc_afreq_6,cc_bfreq_6;
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ClockSameDomain CheckPClock_inst_6(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (first_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_6),
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/* output logic */ .same (cc_same_6),
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/* output integer */ .aFreqK (cc_afreq_6),
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/* output integer */ .bFreqK (cc_bfreq_6)
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initial begin
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wait(
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assert(
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wait(cc_done_6);
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assert(cc_same_6)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_6, 1000000.0/cc_bfreq_6);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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//---<< CheckClock >>----------------
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integer
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ClockSameDomain
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logic cc_done_7,cc_same_7;
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integer cc_afreq_7,cc_bfreq_7;
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ClockSameDomain CheckPClock_inst_7(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (end_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_7),
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/* output logic */ .same (cc_same_7),
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/* output integer */ .aFreqK (cc_afreq_7),
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/* output integer */ .bFreqK (cc_bfreq_7)
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initial begin
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wait(
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assert(
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wait(cc_done_7);
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assert(cc_same_7)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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descript:
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author : Cook.Darwin
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Version: VERC.0.0
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creaded:
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madified:
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***********************************************/
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`timescale 1ns/1ps
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@@ -45,7 +45,7 @@ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) or
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
|
48
|
-
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1))
|
|
48
|
+
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR325 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
|
|
49
49
|
//==========================================================================
|
|
50
50
|
//-------- instance --------------------------------------------------------
|
|
51
51
|
axis_pipe_sync_seam #(
|
|
@@ -122,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
|
|
|
122
122
|
axis_head_cut_verb last_cut_inst(
|
|
123
123
|
/* input */.length (16'd1 ),
|
|
124
124
|
/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
|
|
125
|
-
/* axi_stream_inf.master */.axis_out (
|
|
125
|
+
/* axi_stream_inf.master */.axis_out (out_inf_branchR325 )
|
|
126
126
|
);
|
|
127
127
|
//==========================================================================
|
|
128
128
|
//-------- expression ------------------------------------------------------
|
|
@@ -136,7 +136,7 @@ axis_direct axis_direct_out_inf_inst0 (
|
|
|
136
136
|
);
|
|
137
137
|
|
|
138
138
|
axis_direct axis_direct_out_inf_inst1 (
|
|
139
|
-
/* axi_stream_inf.slaver*/ .slaver (
|
|
139
|
+
/* axi_stream_inf.slaver*/ .slaver (out_inf_branchR325),
|
|
140
140
|
/* axi_stream_inf.master*/ .master (sub_out_inf[1])
|
|
141
141
|
);
|
|
142
142
|
|
|
@@ -26,6 +26,8 @@ module parse_big_field_table_verb #(
|
|
|
26
26
|
axi_stream_inf.mirror cm_mirror
|
|
27
27
|
);
|
|
28
28
|
|
|
29
|
+
localparam VSIZE = $clog2(FIELD_LEN);
|
|
30
|
+
|
|
29
31
|
import SystemPkg::*;
|
|
30
32
|
|
|
31
33
|
initial begin
|
|
@@ -78,13 +80,13 @@ always_ff@(posedge clock,negedge rst_n)begin
|
|
|
78
80
|
else begin
|
|
79
81
|
if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
|
|
80
82
|
region_valid <= 1'b1;
|
|
81
|
-
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
|
|
83
|
+
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
|
|
82
84
|
region_valid <= 1'b0;
|
|
83
85
|
else region_valid <= region_valid;
|
|
84
86
|
end
|
|
85
87
|
end
|
|
86
88
|
|
|
87
|
-
|
|
89
|
+
|
|
88
90
|
logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
|
|
89
91
|
|
|
90
92
|
always_ff@(posedge clock,negedge rst_n)begin
|
|
@@ -107,7 +109,7 @@ always_ff@(posedge clock,negedge rst_n)begin
|
|
|
107
109
|
if(out_valid)
|
|
108
110
|
out_valid <= 1'b0;
|
|
109
111
|
else out_valid <= 1'b1;
|
|
110
|
-
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
|
|
112
|
+
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
|
|
111
113
|
out_valid <= 1'b1;
|
|
112
114
|
else if(region_valid)
|
|
113
115
|
out_valid <= 1'b0;
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
|
|
8
|
+
creaded:
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
|
|
|
48
48
|
endgenerate
|
|
49
49
|
//-------- CLOCKs Total 2 ----------------------
|
|
50
50
|
//--->> CheckClock <<----------------
|
|
51
|
-
logic
|
|
52
|
-
integer
|
|
53
|
-
ClockSameDomain
|
|
51
|
+
logic cc_done_8,cc_same_8;
|
|
52
|
+
integer cc_afreq_8,cc_bfreq_8;
|
|
53
|
+
ClockSameDomain CheckPClock_inst_8(
|
|
54
54
|
/* input */ .aclk (in_inf.clock ),
|
|
55
55
|
/* input */ .bclk (out_inf.clock ),
|
|
56
|
-
/* output logic */ .done (
|
|
57
|
-
/* output logic */ .same (
|
|
58
|
-
/* output integer */ .aFreqK (
|
|
59
|
-
/* output integer */ .bFreqK (
|
|
56
|
+
/* output logic */ .done (cc_done_8),
|
|
57
|
+
/* output logic */ .same (cc_same_8),
|
|
58
|
+
/* output integer */ .aFreqK (cc_afreq_8),
|
|
59
|
+
/* output integer */ .bFreqK (cc_bfreq_8)
|
|
60
60
|
);
|
|
61
61
|
|
|
62
62
|
initial begin
|
|
63
|
-
wait(
|
|
64
|
-
assert(
|
|
63
|
+
wait(cc_done_8);
|
|
64
|
+
assert(cc_same_8)
|
|
65
65
|
else begin
|
|
66
|
-
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/
|
|
66
|
+
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
|
|
67
67
|
repeat(10)begin
|
|
68
68
|
@(posedge in_inf.clock);
|
|
69
69
|
end
|
data/lib/axi_tdl.rb
CHANGED
|
@@ -4,7 +4,7 @@ require "tdl/tdl.rb"
|
|
|
4
4
|
module AxiTdl
|
|
5
5
|
AXI_PATH = File.expand_path(File.join(__dir__,"axi"))
|
|
6
6
|
TDL_PATH = File.expand_path(File.join(__dir__,"tdl"))
|
|
7
|
-
PUBLIC_ATOM_PATH = File.expand_path(File.join(__dir__,"
|
|
7
|
+
PUBLIC_ATOM_PATH = File.expand_path(File.join(__dir__,"public_atom_module"))
|
|
8
8
|
end
|
|
9
9
|
|
|
10
10
|
|
|
@@ -37,7 +37,7 @@ TopModule.contain_hdl("CheckPClock.sv","edge_generator.v","ClockSameDomain.sv","
|
|
|
37
37
|
### 这里引入可能不合适
|
|
38
38
|
TopModule.contain_hdl('axis_full_to_data_c.sv','data_c_pipe_inf.sv','data_c_to_axis_full.sv')
|
|
39
39
|
TopModule.contain_hdl('axi_stream_interconnect_M2S_A1.sv', 'data_c_pipe_intc_M2S_best_last.sv',"data_pipe_interconnect_S2M_verb.sv","data_valve.sv")
|
|
40
|
-
TopModule.contain_hdl('axis_direct_A1.sv',"axis_direct.sv")
|
|
40
|
+
TopModule.contain_hdl('axis_direct_A1.sv',"axis_direct.sv", 'axi4_direct_A1.sv')
|
|
41
41
|
TopModule.contain_hdl 'axi_stream_interconnect_M2S.sv','data_pipe_interconnect_M2S_verb.sv'
|
|
42
42
|
# TopModule.contain_hdl('simple_data_pipe.sv')
|
|
43
43
|
TopModule.contain_hdl('long_fifo_verb.sv',"long_fifo_4bit.sv","long_fifo_4bit_SL8192.sv","long_fifo_4bit_8192.sv","wide_fifo.sv","wide_fifo_7series.sv")
|
data/lib/axi_tdl/version.rb
CHANGED
|
@@ -2,13 +2,12 @@
|
|
|
2
2
|
|
|
3
3
|
class AutoGenSdl
|
|
4
4
|
attr_accessor :bad
|
|
5
|
-
def initialize(filename="",out_file_path=@@auto_path,
|
|
5
|
+
def initialize(filename="",out_file_path=@@auto_path,encoding='utf-8')
|
|
6
6
|
@expand_path = File.expand_path(filename)
|
|
7
7
|
sf = File.open(filename,"r")
|
|
8
|
-
fstr = sf.read.force_encoding(
|
|
8
|
+
fstr = sf.read.force_encoding(encoding)
|
|
9
9
|
sf.close
|
|
10
10
|
@bad = true
|
|
11
|
-
|
|
12
11
|
# return if exist_origin_sdl(filename,@expand_path)
|
|
13
12
|
# fstr.gsub!(/\/\/\s*\(\*\s*show\s*=\s*"false"\s*\*\)/,"(* show = \"false\" *)")
|
|
14
13
|
# SDL ignore `show`
|
|
@@ -1,5 +1,5 @@
|
|
|
1
1
|
$__contain_hdl__ = []
|
|
2
|
-
def __require_hdl__(hdl_path,current_sdlm=nil)
|
|
2
|
+
def __require_hdl__(hdl_path,current_sdlm=nil,encoding='utf-8')
|
|
3
3
|
basename = File.basename(hdl_path,".*")
|
|
4
4
|
unless SdlModule.exist_module? basename
|
|
5
5
|
## 检测是不是全路径, 或当前路径查得到
|
|
@@ -12,7 +12,7 @@ def __require_hdl__(hdl_path,current_sdlm=nil)
|
|
|
12
12
|
raise TdlError.new("Cant find <#{hdl_path}> in tdl paths !!!")
|
|
13
13
|
end
|
|
14
14
|
|
|
15
|
-
AutoGenSdl.new(rel,File.join(__dir__,"tmp")).auto_rb
|
|
15
|
+
AutoGenSdl.new(rel,File.join(__dir__,"tmp"),encoding=encoding).auto_rb
|
|
16
16
|
|
|
17
17
|
## 如果是 在非 sdlmodule 内引用需要添加contain_hdl
|
|
18
18
|
# if !(current_sdlm.is_a?(SdlModule))
|
|
@@ -65,6 +65,6 @@ def find_first_hdl_path(basename)
|
|
|
65
65
|
return nil
|
|
66
66
|
end
|
|
67
67
|
|
|
68
|
-
def require_hdl(hdl_path)
|
|
69
|
-
__require_hdl__(hdl_path,nil)
|
|
68
|
+
def require_hdl(hdl_path,encoding='utf-8')
|
|
69
|
+
__require_hdl__(hdl_path,nil,encoding)
|
|
70
70
|
end
|
|
@@ -89,7 +89,7 @@ module ClassHDL
|
|
|
89
89
|
str.push op.instance(:always_ff).gsub(/^./){ |m| " #{m}"}
|
|
90
90
|
else
|
|
91
91
|
unless op.slaver
|
|
92
|
-
rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
|
|
92
|
+
rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff,belong_to_module))
|
|
93
93
|
str.push " #{rel_str};"
|
|
94
94
|
end
|
|
95
95
|
end
|
|
@@ -70,7 +70,7 @@ module ClassHDL
|
|
|
70
70
|
def ELSIF(cond,&block)
|
|
71
71
|
if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? HDLAssignGenerateBlock
|
|
72
72
|
if cond.respond_to?(:instance)
|
|
73
|
-
head_str = "else if(#{cond.instance(:cond)})begin\n"
|
|
73
|
+
head_str = "else if(#{cond.instance(:cond,@belong_to_module)})begin\n"
|
|
74
74
|
else
|
|
75
75
|
head_str = "else if(#{cond})begin\n"
|
|
76
76
|
end
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-05-
|
|
8
|
+
created: 2021-05-30 12:21:35 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -19,7 +19,7 @@ module test_module_var #(
|
|
|
19
19
|
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
|
-
localparam ASIZE = 20;
|
|
22
|
+
localparam ASIZE = 20 ;
|
|
23
23
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
24
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
25
25
|
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|
|
@@ -12,128 +12,8 @@ gui_set_time_units 1ps
|
|
|
12
12
|
## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
|
|
13
13
|
## ==== [add_signal] ===== ##
|
|
14
14
|
|
|
15
|
-
## -------------- sub_md0_logic -------------------------
|
|
16
|
-
set _wave_session_group_sub_md0_logic sub_md0_logic
|
|
17
|
-
# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
|
|
18
|
-
if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
|
|
19
|
-
set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
|
|
20
|
-
}
|
|
21
|
-
set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
|
|
22
|
-
|
|
23
|
-
## 添加信号到 group
|
|
24
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt} }
|
|
25
|
-
## ============== sub_md0_logic =========================
|
|
26
|
-
|
|
27
|
-
|
|
28
|
-
## -------------- sub_md0_interface -------------------------
|
|
29
|
-
set _wave_session_group_sub_md0_interface sub_md0_interface
|
|
30
|
-
# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
|
|
31
|
-
if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
|
|
32
|
-
set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
|
|
33
|
-
}
|
|
34
|
-
set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
|
|
35
|
-
|
|
36
|
-
## 添加信号到 group
|
|
37
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in} }
|
|
38
|
-
## ============== sub_md0_interface =========================
|
|
39
|
-
|
|
40
|
-
|
|
41
|
-
## -------------- sub_md0_default -------------------------
|
|
42
|
-
set _wave_session_group_sub_md0_default sub_md0_default
|
|
43
|
-
# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
|
|
44
|
-
if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
|
|
45
|
-
set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
|
|
46
|
-
}
|
|
47
|
-
set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
|
|
48
|
-
|
|
49
|
-
## 添加信号到 group
|
|
50
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
|
|
51
|
-
## ============== sub_md0_default =========================
|
|
52
|
-
|
|
53
|
-
|
|
54
|
-
## -------------- sub_md0_default.inter_tf -------------------------
|
|
55
|
-
## set _wave_session_group_sub_md0_default_inter_tf Group1
|
|
56
|
-
## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
|
|
57
15
|
|
|
58
|
-
set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
|
|
59
|
-
append _wave_session_group_sub_md0_default_inter_tf inter_tf
|
|
60
|
-
set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
|
|
61
|
-
|
|
62
|
-
# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
|
|
63
|
-
|
|
64
|
-
## 添加信号到 group
|
|
65
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf} }
|
|
66
|
-
## ============== sub_md0_default.inter_tf =========================
|
|
67
|
-
|
|
68
|
-
|
|
69
|
-
## -------------- sub_md1_default -------------------------
|
|
70
|
-
set _wave_session_group_sub_md1_default sub_md1_default
|
|
71
|
-
# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
|
|
72
|
-
if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
|
|
73
|
-
set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
|
|
74
|
-
}
|
|
75
|
-
set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
|
|
76
|
-
|
|
77
|
-
## 添加信号到 group
|
|
78
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable} }
|
|
79
|
-
## ============== sub_md1_default =========================
|
|
80
|
-
|
|
81
|
-
|
|
82
|
-
## -------------- sub_md1_inner -------------------------
|
|
83
|
-
set _wave_session_group_sub_md1_inner sub_md1_inner
|
|
84
|
-
# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
|
|
85
|
-
if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
|
|
86
|
-
set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
|
|
87
|
-
}
|
|
88
|
-
set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
|
|
89
|
-
|
|
90
|
-
## 添加信号到 group
|
|
91
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
|
|
92
|
-
## ============== sub_md1_inner =========================
|
|
93
|
-
|
|
94
16
|
|
|
95
|
-
## -------------- sub_md1_inner.inter_tf -------------------------
|
|
96
|
-
## set _wave_session_group_sub_md1_inner_inter_tf Group1
|
|
97
|
-
## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
|
|
98
|
-
|
|
99
|
-
set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
|
|
100
|
-
append _wave_session_group_sub_md1_inner_inter_tf inter_tf
|
|
101
|
-
set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
|
|
102
|
-
|
|
103
|
-
# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
|
|
104
|
-
|
|
105
|
-
## 添加信号到 group
|
|
106
|
-
gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf} }
|
|
107
|
-
## ============== sub_md1_inner.inter_tf =========================
|
|
108
|
-
|
|
109
|
-
|
|
110
|
-
## -------------- exp_test_unit_default -------------------------
|
|
111
|
-
set _wave_session_group_exp_test_unit_default exp_test_unit_default
|
|
112
|
-
# set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
|
|
113
|
-
if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
|
|
114
|
-
set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
|
|
115
|
-
}
|
|
116
|
-
set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
|
|
117
|
-
|
|
118
|
-
## 添加信号到 group
|
|
119
|
-
gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" { }
|
|
120
|
-
## ============== exp_test_unit_default =========================
|
|
121
|
-
|
|
122
|
-
|
|
123
|
-
## -------------- exp_test_unit_default.axis_data_inf -------------------------
|
|
124
|
-
## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
|
|
125
|
-
## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
|
|
126
|
-
|
|
127
|
-
set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
|
|
128
|
-
append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
|
|
129
|
-
set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
|
|
130
|
-
|
|
131
|
-
# set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
|
|
132
|
-
|
|
133
|
-
## 添加信号到 group
|
|
134
|
-
gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" { {Sim:tb_exp_test_unit.rtl_top.axis_data_inf} }
|
|
135
|
-
## ============== exp_test_unit_default.axis_data_inf =========================
|
|
136
|
-
|
|
137
17
|
|
|
138
18
|
## 创建波形窗口
|
|
139
19
|
if {![info exists useOldWindow]} {
|
|
@@ -162,33 +42,9 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
|
|
|
162
42
|
## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
|
|
163
43
|
## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
|
|
164
44
|
## === [add_signal_wave] === ##
|
|
165
|
-
|
|
166
|
-
|
|
167
|
-
|
|
168
|
-
## -------------- Group2_sub_md0_interface -------------------------
|
|
169
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
|
|
170
|
-
## ============== Group2_sub_md0_interface =========================
|
|
171
|
-
## -------------- Group2_sub_md0_default -------------------------
|
|
172
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
|
|
173
|
-
## ============== Group2_sub_md0_default =========================
|
|
174
|
-
## -------------- sub_md0_default|inter_tf -------------------------
|
|
175
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
|
|
176
|
-
## ============== sub_md0_default|inter_tf =========================
|
|
177
|
-
## -------------- Group2_sub_md1_default -------------------------
|
|
178
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
|
|
179
|
-
## ============== Group2_sub_md1_default =========================
|
|
180
|
-
## -------------- Group2_sub_md1_inner -------------------------
|
|
181
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
|
|
182
|
-
## ============== Group2_sub_md1_inner =========================
|
|
183
|
-
## -------------- sub_md1_inner|inter_tf -------------------------
|
|
184
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
|
|
185
|
-
## ============== sub_md1_inner|inter_tf =========================
|
|
186
|
-
## -------------- Group2_exp_test_unit_default -------------------------
|
|
187
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
|
|
188
|
-
## ============== Group2_exp_test_unit_default =========================
|
|
189
|
-
## -------------- exp_test_unit_default|axis_data_inf -------------------------
|
|
190
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
|
|
191
|
-
## ============== exp_test_unit_default|axis_data_inf =========================
|
|
45
|
+
|
|
46
|
+
|
|
47
|
+
|
|
192
48
|
|
|
193
49
|
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
|
194
50
|
|
|
@@ -205,12 +61,9 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
|
|
|
205
61
|
gui_list_set_filter -id ${Wave.3} -text {*}
|
|
206
62
|
##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
|
|
207
63
|
## === [add_bar] === ##
|
|
208
|
-
|
|
209
|
-
|
|
210
|
-
|
|
211
|
-
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
|
|
212
|
-
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
|
|
213
|
-
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_default} -position in
|
|
64
|
+
|
|
65
|
+
|
|
66
|
+
|
|
214
67
|
|
|
215
68
|
gui_marker_move -id ${Wave.3} {C1} 560248001
|
|
216
69
|
gui_view_scroll -id ${Wave.3} -vertical -set 35
|
|
@@ -1,9 +1,28 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2021-05-30 12:21:54 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
12
|
+
|
|
13
|
+
module test_top (
|
|
14
|
+
input sys_clock,
|
|
15
|
+
output logic[3:0] odata
|
|
16
|
+
);
|
|
17
|
+
|
|
18
|
+
//==========================================================================
|
|
19
|
+
//-------- define ----------------------------------------------------------
|
|
20
|
+
|
|
21
|
+
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
|
|
25
|
+
//==========================================================================
|
|
26
|
+
//-------- expression ------------------------------------------------------
|
|
27
|
+
|
|
9
28
|
endmodule
|
|
@@ -1,28 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2021-05-04 20:03:49 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module test_top_sim (
|
|
14
|
-
input sys_clock,
|
|
15
|
-
output logic[3:0] odata
|
|
16
|
-
);
|
|
17
|
-
|
|
18
|
-
//==========================================================================
|
|
19
|
-
//-------- define ----------------------------------------------------------
|
|
20
|
-
|
|
21
|
-
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
|
|
25
|
-
//==========================================================================
|
|
26
|
-
//-------- expression ------------------------------------------------------
|
|
27
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module test_top_sim();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
28
9
|
endmodule
|
metadata
CHANGED
|
@@ -1,14 +1,14 @@
|
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
|
2
2
|
name: axi_tdl
|
|
3
3
|
version: !ruby/object:Gem::Version
|
|
4
|
-
version: 0.1.
|
|
4
|
+
version: 0.1.8
|
|
5
5
|
platform: ruby
|
|
6
6
|
authors:
|
|
7
7
|
- Cook.Darwin
|
|
8
8
|
autorequire:
|
|
9
9
|
bindir: exe
|
|
10
10
|
cert_chain: []
|
|
11
|
-
date: 2021-05-
|
|
11
|
+
date: 2021-05-30 00:00:00.000000000 Z
|
|
12
12
|
dependencies:
|
|
13
13
|
- !ruby/object:Gem::Dependency
|
|
14
14
|
name: rake
|