axi_tdl 0.1.5 → 0.1.7

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Files changed (60) hide show
  1. checksums.yaml +4 -4
  2. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  3. data/lib/axi/AXI4/axi4_dpram_cache.sv +9 -9
  4. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  5. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  6. data/lib/axi/AXI4/axis_to_axi4_wr.sv +12 -12
  7. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  8. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
  9. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +27 -27
  10. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +11 -11
  11. data/lib/axi/AXI_stream/axis_insert_copy.sv +2 -2
  12. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +3 -3
  13. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +5 -5
  14. data/lib/axi/AXI_stream/axis_sim_master_model.sv +2 -2
  15. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +2 -2
  16. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  17. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  18. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +3 -3
  19. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  20. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  21. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  22. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  23. data/lib/axi_tdl.rb +31 -1
  24. data/lib/axi_tdl/version.rb +1 -1
  25. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  26. data/lib/tdl/auto_script/import_hdl.rb +39 -4
  27. data/lib/tdl/axi4/axi4_interconnect_verb.rb +1 -1
  28. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  29. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +33 -7
  30. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +7 -33
  31. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  32. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  33. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -2
  34. data/lib/tdl/examples/11_test_unit/tu0.sv +5 -4
  35. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  36. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  37. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  38. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  39. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  40. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
  41. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  42. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +6 -6
  43. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  44. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  45. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  46. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  47. data/lib/tdl/examples/8_top_module/dve.tcl +153 -6
  48. data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
  49. data/lib/tdl/examples/8_top_module/test_top_sim.sv +26 -7
  50. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
  51. data/lib/tdl/examples/9_itegration/dve.tcl +29 -29
  52. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +2 -2
  53. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  54. data/lib/tdl/exlib/itegration_verb.rb +45 -39
  55. data/lib/tdl/rebuild_ele/ele_base.rb +7 -2
  56. data/lib/tdl/sdlmodule/sdlmodule.rb +56 -0
  57. data/lib/tdl/sdlmodule/test_unit_module.rb +1 -0
  58. data/lib/tdl/sdlmodule/top_module.rb +4 -0
  59. data/lib/tdl/tdl.rb +1 -1
  60. metadata +5 -3
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: '048d045e78b400e945ff441c154ef78f8073619c51a1547e84526cb9345d72f4'
4
- data.tar.gz: baa90f99cf5d67251033740eb77a6314a74b445520159da7fba098d57cffd7f7
3
+ metadata.gz: 8dcdd989e2689e971fc985667c17515a0aeb471fab48e714711090b47163bdd1
4
+ data.tar.gz: c1aca96af70b0186764d985bc2b4f12bc5227c8a2ed46c9b309a05b3d6028a0e
5
5
  SHA512:
6
- metadata.gz: 95f82468aeffc02b0c0bc09574d9805eef139180474f02a736fb85f8081a874947eb9d4730ebca7197e5d2051c9d8c73f8404b2732d1b3810eab9e4ffbf4cd71
7
- data.tar.gz: ec8a233a0df4d3b6f47f4a5078f08ee538acf7153e09c62d0cba18f4e95bcecfca253c211cfa298d51d3486686bb9c487a3e5cbc45b41d2f699c90ac5c36d95a
6
+ metadata.gz: 24e9e8b96ea593632f9ea630711f6ce8f08dec4da1ef97b3866ec11f7853e4398dfa716529ef8be952e6cc27154514245877293b7a168e7b7e4d73f045e306f9
7
+ data.tar.gz: 427854dbe9daa78df1ffbea9491da18d6456e261812b7b0bdc2dd131b28f7c4cf379baa6a34957704a3dcfb8fb8b7ff68a7cba6b9378fdd92bc24cfb230df940
data/lib/axi/AXI4/axi4_dpram_cache.rb CHANGED
@@ -4,6 +4,7 @@ require_sdl 'common_ram_wrapper.rb'
4
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5
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  require_hdl File.join(__dir__,"./full_axi4_to_axis.sv")
6
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  require_hdl 'data_inf_c_planer_A1.sv'
7
+ data_inf_c_planer_A1.contain_hdl 'data_inf_planer_A1.sv'
7
8
 
8
9
  TdlBuild.axi4_dpram_cache(__dir__) do
9
10
  parameter.INIT_FILE ''
data/lib/axi/AXI4/axi4_dpram_cache.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
6
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  author : Cook.Darwin
7
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  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
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+ created: 2021-04-16 17:01:03 +0800
9
9
  madified:
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  ***********************************************/
11
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  `timescale 1ns/1ps
@@ -21,14 +21,14 @@ module axi4_dpram_cache #(
21
21
  //-------- define ----------------------------------------------------------
22
22
 
23
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  cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE((a_inf.DSIZE / 8))) xram_inf();
24
- axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
25
- axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
26
- data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
27
- data_inf_c #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1)) a_datac_rd_rel_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
28
- axi_stream_inf #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1),.USIZE(1)) b_axis_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
29
- axi_stream_inf #(.DSIZE(b_inf.DSIZE),.USIZE(1)) b_axis_rd_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
30
- data_inf_c #(.DSIZE(b_inf.ASIZE+1)) b_datac_rd_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
31
- data_inf_c #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1)) b_datac_rd_rel_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
24
+ axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.FreqM(1.0),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
25
+ axi_stream_inf #(.DSIZE(a_inf.DSIZE),.FreqM(1.0),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
26
+ data_inf_c #(.DSIZE(a_inf.ASIZE+1),.FreqM(1.0)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
27
+ data_inf_c #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.FreqM(1.0)) a_datac_rd_rel_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
28
+ axi_stream_inf #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1),.FreqM(1.0),.USIZE(1)) b_axis_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
29
+ axi_stream_inf #(.DSIZE(b_inf.DSIZE),.FreqM(1.0),.USIZE(1)) b_axis_rd_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
30
+ data_inf_c #(.DSIZE(b_inf.ASIZE+1),.FreqM(1.0)) b_datac_rd_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
31
+ data_inf_c #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1),.FreqM(1.0)) b_datac_rd_rel_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
32
32
  //==========================================================================
33
33
  //-------- instance --------------------------------------------------------
34
34
  full_axi4_to_axis full_axi4_to_axis_ainst(
data/lib/axi/AXI4/axi4_rd_burst_track.sv CHANGED
@@ -16,7 +16,8 @@ module axi4_rd_burst_track #(
16
16
  )(
17
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  axi_inf.mirror_rd axi4_mirror
18
18
  );
19
- import GlobalPkg::*;
19
+ // import GlobalPkg::*;
20
+ import SystemPkg::*;
20
21
 
21
22
  logic LSIZE =
22
23
  (axi4_mirror.IDSIZE>= 37 )? 9 : //
data/lib/axi/AXI4/axi4_wr_burst_track.sv CHANGED
@@ -16,7 +16,8 @@ module axi4_wr_burst_track #(
16
16
  axi_inf.mirror_wr axi4_mirror
17
17
  );
18
18
 
19
- import GlobalPkg::*;
19
+ // import GlobalPkg::*;
20
+ import SystemPkg::*;
20
21
 
21
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  logic LSIZE =
22
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  (axi4_mirror.IDSIZE>= 37 )? 9 : //
data/lib/axi/AXI4/axis_to_axi4_wr.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
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  descript:
6
6
  author : Cook.Darwin
7
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  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
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+ created: xxxx.xx.xx
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  madified:
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  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -53,11 +53,11 @@ logic rd_en;
53
53
  logic fifo_empty;
54
54
  logic fifo_full;
55
55
  logic stream_en;
56
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
- axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
- axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R186 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
56
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
+ axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
+ axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1138 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
61
61
  //==========================================================================
62
62
  //-------- instance --------------------------------------------------------
63
63
  axis_length_split_with_addr #(
@@ -92,16 +92,16 @@ independent_clock_fifo #(
92
92
  /* output */.full (fifo_full )
93
93
  );
94
94
  axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
95
- /* output */.stream_en (stream_en ),
96
- /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
97
- /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R186 )
95
+ /* output */.stream_en (stream_en ),
96
+ /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
97
+ /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1138 )
98
98
  );
99
99
  vcs_axi4_comptable #(
100
100
  .ORIGIN ("master_wr_aux_no_resp" ),
101
101
  .TO ("master_wr" )
102
- )vcs_axi4_comptable_axi_wr_aux_R282_axi_wr_inst(
103
- /* input */.origin (axi_wr_vcs_cp_R186 ),
104
- /* output */.to (axi_wr )
102
+ )vcs_axi4_comptable_axi_wr_aux_R1044_axi_wr_inst(
103
+ /* input */.origin (axi_wr_vcs_cp_R1138 ),
104
+ /* output */.to (axi_wr )
105
105
  );
106
106
  axis_valve_with_pipe #(
107
107
  .MODE ("BOTH" )
data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
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  descript:
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6
  author : Cook.Darwin
7
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  Version: VERA.0.0
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- creaded: XXXX.XX.XX
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+ created: 2021-04-16 17:26:51 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -23,10 +23,10 @@ logic clock;
23
23
  logic rst_n;
24
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  (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
25
25
  (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
26
- data_inf_c #(.DSIZE(long_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE)) pre_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
27
- data_inf_c #(.DSIZE(short_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE)) post_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
28
- data_inf_c #(.DSIZE(1)) partition_pulse_inf (.clock(clock),.rst_n(rst_n)) ;
29
- data_inf_c #(.DSIZE(1)) wait_last_inf (.clock(clock),.rst_n(rst_n)) ;
26
+ data_inf_c #(.DSIZE(long_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE),.FreqM(long_inf.FreqM)) pre_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
27
+ data_inf_c #(.DSIZE(short_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE),.FreqM(long_inf.FreqM)) post_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
28
+ data_inf_c #(.DSIZE(1),.FreqM(long_inf.FreqM)) partition_pulse_inf (.clock(clock),.rst_n(rst_n)) ;
29
+ data_inf_c #(.DSIZE(1),.FreqM(long_inf.FreqM)) wait_last_inf (.clock(clock),.rst_n(rst_n)) ;
30
30
  //==========================================================================
31
31
  //-------- instance --------------------------------------------------------
32
32
  data_inf_partition #(
data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
8
+ created: XXXX.XX.XX
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -53,11 +53,11 @@ logic fifo_rd_en;
53
53
  logic fifo_empty;
54
54
  logic fifo_full;
55
55
  logic stream_en;
56
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
- axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
- axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1342 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
56
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
+ axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
+ axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R555 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
61
61
  //==========================================================================
62
62
  //-------- instance --------------------------------------------------------
63
63
  axis_length_split_with_addr #(
@@ -91,16 +91,16 @@ independent_clock_fifo #(
91
91
  /* output */.full (fifo_full )
92
92
  );
93
93
  axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
94
- /* output */.stream_en (stream_en ),
95
- /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
96
- /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1342 )
94
+ /* output */.stream_en (stream_en ),
95
+ /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
96
+ /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R555 )
97
97
  );
98
98
  vcs_axi4_comptable #(
99
99
  .ORIGIN ("master_wr_aux_no_resp" ),
100
100
  .TO ("master_wr" )
101
- )vcs_axi4_comptable_axi_wr_aux_R700_axi_wr_inst(
102
- /* input */.origin (axi_wr_vcs_cp_R1342 ),
103
- /* output */.to (axi_wr )
101
+ )vcs_axi4_comptable_axi_wr_aux_R478_axi_wr_inst(
102
+ /* input */.origin (axi_wr_vcs_cp_R555 ),
103
+ /* output */.to (axi_wr )
104
104
  );
105
105
  axis_valve_with_pipe #(
106
106
  .MODE ("OUT" )
data/lib/axi/AXI_stream/axi_stream_split_channel.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-04-03 14:03:22 +0800
8
+ created: 2021-04-16 17:01:05 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,8 +23,8 @@ logic clock;
23
23
  logic rst_n;
24
24
  logic addr;
25
25
  logic new_last;
26
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
27
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
26
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
27
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
28
28
  //==========================================================================
29
29
  //-------- instance --------------------------------------------------------
30
30
  axi_stream_interconnect_S2M #(
@@ -55,22 +55,22 @@ axis_direct axis_direct_end_inf_inst0 (
55
55
  );
56
56
  //-------- CLOCKs Total 3 ----------------------
57
57
  //--->> CheckClock <<----------------
58
- logic cc_done_0,cc_same_0;
59
- integer cc_afreq_0,cc_bfreq_0;
60
- ClockSameDomain CheckPClock_inst_0(
61
- /* input */ .aclk (origin_inf.aclk),
62
- /* input */ .bclk (first_inf.aclk),
63
- /* output logic */ .done (cc_done_0),
64
- /* output logic */ .same (cc_same_0),
65
- /* output integer */ .aFreqK (cc_afreq_0),
66
- /* output integer */ .bFreqK (cc_bfreq_0)
58
+ logic cc_done_7,cc_same_7;
59
+ integer cc_afreq_7,cc_bfreq_7;
60
+ ClockSameDomain CheckPClock_inst_7(
61
+ /* input */ .aclk (origin_inf.aclk ),
62
+ /* input */ .bclk (first_inf.aclk ),
63
+ /* output logic */ .done (cc_done_7),
64
+ /* output logic */ .same (cc_same_7),
65
+ /* output integer */ .aFreqK (cc_afreq_7),
66
+ /* output integer */ .bFreqK (cc_bfreq_7)
67
67
  );
68
68
 
69
69
  initial begin
70
- wait(cc_done_0);
71
- assert(cc_same_0)
70
+ wait(cc_done_7);
71
+ assert(cc_same_7)
72
72
  else begin
73
- $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_0, 1000000.0/cc_bfreq_0);
73
+ $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
74
74
  repeat(10)begin
75
75
  @(posedge origin_inf.aclk);
76
76
  end
@@ -80,22 +80,22 @@ end
80
80
  //---<< CheckClock >>----------------
81
81
 
82
82
  //--->> CheckClock <<----------------
83
- logic cc_done_1,cc_same_1;
84
- integer cc_afreq_1,cc_bfreq_1;
85
- ClockSameDomain CheckPClock_inst_1(
86
- /* input */ .aclk (origin_inf.aclk),
87
- /* input */ .bclk (end_inf.aclk),
88
- /* output logic */ .done (cc_done_1),
89
- /* output logic */ .same (cc_same_1),
90
- /* output integer */ .aFreqK (cc_afreq_1),
91
- /* output integer */ .bFreqK (cc_bfreq_1)
83
+ logic cc_done_8,cc_same_8;
84
+ integer cc_afreq_8,cc_bfreq_8;
85
+ ClockSameDomain CheckPClock_inst_8(
86
+ /* input */ .aclk (origin_inf.aclk ),
87
+ /* input */ .bclk (end_inf.aclk ),
88
+ /* output logic */ .done (cc_done_8),
89
+ /* output logic */ .same (cc_same_8),
90
+ /* output integer */ .aFreqK (cc_afreq_8),
91
+ /* output integer */ .bFreqK (cc_bfreq_8)
92
92
  );
93
93
 
94
94
  initial begin
95
- wait(cc_done_1);
96
- assert(cc_same_1)
95
+ wait(cc_done_8);
96
+ assert(cc_same_8)
97
97
  else begin
98
- $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_1, 1000000.0/cc_bfreq_1);
98
+ $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
99
99
  repeat(10)begin
100
100
  @(posedge origin_inf.aclk);
101
101
  end
data/lib/axi/AXI_stream/axis_head_cut_verc.sv CHANGED
@@ -4,8 +4,8 @@ ___________ Cook Darwin __________
4
4
  _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
- Version: VERA.0.0
8
- creaded: XXXX.XX.XX
7
+ Version: VERC.0.0
8
+ created: XXXX.XX.XX
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -39,13 +39,13 @@ logic [4-1:0] int_cut_len ;
39
39
  logic [4-1:0] shift_sel_pre ;
40
40
  logic fifo_wr_en_lat;
41
41
  logic [4-1:0] shift_sel ;
42
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
43
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
44
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
45
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
46
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
47
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
48
- axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR774 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
42
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
43
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
44
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
45
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
46
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
47
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
48
+ axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR655 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
49
49
  //==========================================================================
50
50
  //-------- instance --------------------------------------------------------
51
51
  axis_pipe_sync_seam #(
@@ -122,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
122
122
  axis_head_cut_verb last_cut_inst(
123
123
  /* input */.length (16'd1 ),
124
124
  /* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
125
- /* axi_stream_inf.master */.axis_out (out_inf_branchR774 )
125
+ /* axi_stream_inf.master */.axis_out (out_inf_branchR655 )
126
126
  );
127
127
  //==========================================================================
128
128
  //-------- expression ------------------------------------------------------
@@ -136,7 +136,7 @@ axis_direct axis_direct_out_inf_inst0 (
136
136
  );
137
137
 
138
138
  axis_direct axis_direct_out_inf_inst1 (
139
- /* axi_stream_inf.slaver*/ .slaver (out_inf_branchR774),
139
+ /* axi_stream_inf.slaver*/ .slaver (out_inf_branchR655),
140
140
  /* axi_stream_inf.master*/ .master (sub_out_inf[1])
141
141
  );
142
142
 
data/lib/axi/AXI_stream/axis_insert_copy.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
8
+ created: 2021-04-16 17:01:06 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -22,7 +22,7 @@ module axis_insert_copy (
22
22
  logic clock;
23
23
  logic rst_n;
24
24
  logic insert_tri;
25
- axi_stream_inf #(.DSIZE(in_inf.DSIZE),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
25
+ axi_stream_inf #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
26
26
  //==========================================================================
27
27
  //-------- instance --------------------------------------------------------
28
28
  axis_connect_pipe axis_connect_pipe_inst(
data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
8
+ created: 2021-04-16 17:01:05 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,8 +23,8 @@ module axis_pipe_sync_seam #(
23
23
  //==========================================================================
24
24
  //-------- define ----------------------------------------------------------
25
25
 
26
- data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
27
- data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
26
+ data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(1.0)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
27
+ data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(data_in_inf.FreqM)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
28
28
  //==========================================================================
29
29
  //-------- instance --------------------------------------------------------
30
30
  data_c_pipe_sync_seam #(
data/lib/axi/AXI_stream/axis_rom_contect_sim.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
8
+ created: 2021-04-16 17:01:02 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -25,11 +25,11 @@ module axis_rom_contect_sim #(
25
25
  //==========================================================================
26
26
  //-------- define ----------------------------------------------------------
27
27
 
28
- axi_stream_inf #(.DSIZE((a_axis_zip.DSIZE / 2)),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
29
- axi_stream_inf #(.DSIZE((b_axis_zip.DSIZE / 2)),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
28
+ axi_stream_inf #(.DSIZE((a_axis_zip.DSIZE / 2)),.FreqM(a_axis_zip.FreqM),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
29
+ axi_stream_inf #(.DSIZE((b_axis_zip.DSIZE / 2)),.FreqM(b_axis_zip.FreqM),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
30
30
  cm_ram_inf #(.DSIZE(a_rom_contect_inf.DSIZE),.RSIZE(a_axis_zip.DSIZE),.MSIZE(1)) xram_inf();
31
- axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+(a_axis_zip.DSIZE / 2)),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
32
- axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+(b_axis_zip.DSIZE / 2)),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
31
+ axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+(a_axis_zip.DSIZE / 2)),.FreqM(a_rom_contect_inf.FreqM),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
32
+ axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+(b_axis_zip.DSIZE / 2)),.FreqM(b_rom_contect_inf.FreqM),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
33
33
  //==========================================================================
34
34
  //-------- instance --------------------------------------------------------
35
35
  axis_uncompress_A1 #(
data/lib/axi/AXI_stream/axis_sim_master_model.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-04-03 14:03:22 +0800
8
+ created: 2021-04-16 17:01:07 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -24,7 +24,7 @@ module axis_sim_master_model #(
24
24
  //==========================================================================
25
25
  //-------- define ----------------------------------------------------------
26
26
 
27
- data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
27
+ data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1),.FreqM(1.0)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
28
28
  //==========================================================================
29
29
  //-------- instance --------------------------------------------------------
30
30
  data_c_sim_master_model #(
data/lib/axi/AXI_stream/axis_split_channel_verb.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
8
+ created: 2021-04-16 17:01:06 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,7 +23,7 @@ logic clock;
23
23
  logic rst_n;
24
24
  logic [16-1:0] insert_seed ;
25
25
  logic [16-1:0] next_split_len ;
26
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
26
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
27
27
  //==========================================================================
28
28
  //-------- instance --------------------------------------------------------
29
29
  axis_insert_copy axis_insert_copy_inst(
data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv ADDED
@@ -0,0 +1,50 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded:
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* axi_stream = "true" *)
13
+ module axis_width_convert_verb #(
14
+ parameter IDSIZE = 8,
15
+ parameter ODSIZE = 16
16
+ )(
17
+ axi_stream_inf.slaver in_axis,
18
+ axi_stream_inf.master out_axis
19
+ );
20
+
21
+ generate
22
+ if(IDSIZE == ODSIZE)
23
+ axis_direct_A1 #(
24
+ .IDSIZE (in_axis.DSIZE),
25
+ .ODSIZE (out_axis.DSIZE)
26
+ )axis_direct_A1_inst(
27
+ /* axi_stream_inf.slaver */ .slaver (in_axis ),
28
+ /* axi_stream_inf.master */ .master (out_axis )
29
+ );
30
+ else
31
+ width_convert_verb #(
32
+ .ISIZE (IDSIZE ),
33
+ .OSIZE (ODSIZE )
34
+ )width_convert_verb_inst(
35
+ /* input */ .clock (in_axis.aclk ),
36
+ /* input */ .rst_n (in_axis.aresetn ),
37
+ /* input [ISIZE-1:0] */ .wr_data (in_axis.axis_tdata ),
38
+ /* input */ .wr_vld (in_axis.axis_tvalid ),
39
+ /* output logic */ .wr_ready (in_axis.axis_tready ),
40
+ /* input */ .wr_last (in_axis.axis_tlast ),
41
+ /* input */ .wr_align_last (1'b0), //can be leave 1'b0
42
+ /* output logic[OSIZE-1:0] */ .rd_data (out_axis.axis_tdata ),
43
+ /* output logic */ .rd_vld (out_axis.axis_tvalid ),
44
+ /* input */ .rd_ready (out_axis.axis_tready ),
45
+ /* output */ .rd_last (out_axis.axis_tlast )
46
+ );
47
+
48
+ endgenerate
49
+
50
+ endmodule