aarch64 2.1.0 → 3.0.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: ea2cf209e63aaf787b7a0a05f5d1788c3bfa36f1cee6fa1a812a99e2de5e42eb
-  data.tar.gz: 8d60abcae40ed475e8f3756892f432a88e99501e23f5df2d113e02b64042290f
+  metadata.gz: 87efdbd48c160012a9bb9611a206fddf3bffeac5a748bb6ff8bb489805653f75
+  data.tar.gz: dd78668280e3d37f556f2b103f4cf25c7b8d0bcb696630e507a3c6cd5fae70c4
 SHA512:
-  metadata.gz: 44a6660bab9ee5db6f80b4714e8fc53d64f351f1ba2c9b2293826d83215423944fd8a2b444ea4cded815b09ed70f2bef289eb25ef5ff596dc781ceeb781a4643
-  data.tar.gz: b6e384d4d8743cd74a4324fb7e2e50f1f3317446a8d0ff2518ccecabed09634f8c0126e8831af21e5d57284254e3c9d5f83e578f924bc2e2d84b0f05b6e3ac4a
+  metadata.gz: a0eab1ba04ba42218bcb13c82d38f10315363b8e4598dd75cf73c82f0f3b3665881bc10f32b94ad203a6cd038a2f38d1eb353e528e1b3afe88ee57911e726f07
+  data.tar.gz: d2048034588506baa2d70ca5a5b4fb0352379a9275fc9b0bd9548be96f2754fbac3888691fb1762adab3a81590fbfc27c041b8975db73c67c58a1a9460e96dbe

data/.github/workflows/ci.yml

@@ -0,0 +1,42 @@
+name: CI
+
+on:
+  push:
+  pull_request:
+
+jobs:
+  ruby-versions:
+    uses: ruby/actions/.github/workflows/ruby_versions.yml@master
+    with:
+      engine: cruby
+
+  test:
+    needs: ruby-versions
+    runs-on: ubuntu-24.04-arm
+    strategy:
+      matrix:
+        ruby: ${{ fromJson(needs.ruby-versions.outputs.versions) }}
+
+    steps:
+      - uses: actions/checkout@v4
+      
+      - name: Set up Ruby
+        uses: ruby/setup-ruby-pkgs@v1
+        with:
+          ruby-version: ${{ matrix.ruby }}
+          apt-get: "haveged libyaml-dev cmake g++"
+
+      - name: Build capstone 5 from source
+        run: |
+          git clone --depth 1 --branch 5.0.7 https://github.com/capstone-engine/capstone.git /tmp/capstone
+          cd /tmp/capstone
+          cmake -B build -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -DBUILD_SHARED_LIBS=ON
+          cmake --build build -j$(nproc)
+          sudo cmake --install build
+          sudo ldconfig
+
+      - name: Install dependencies
+        run: bundle install
+
+      - name: Run tests
+        run: bundle exec rake test

data/.github/workflows/release.yml

@@ -0,0 +1,62 @@
+name: Publish gem to rubygems.org
+
+on:
+  push:
+    tags:
+      - 'v*'
+
+permissions:
+  contents: read
+
+jobs:
+  push:
+    if: github.repository == 'tenderlove/aarch64'
+    runs-on: ubuntu-24.04-arm
+
+    environment:
+      name: rubygems.org
+      url: https://rubygems.org/gems/aarch64
+
+    permissions:
+      contents: write
+      id-token: write
+
+    strategy:
+      matrix:
+        ruby: ["ruby"]
+
+    steps:
+      - name: Harden Runner
+        uses: step-security/harden-runner@v2
+        with:
+          egress-policy: audit
+
+      - uses: actions/checkout@v4
+
+      - name: Set up Ruby
+        uses: ruby/setup-ruby@v1
+        with:
+          ruby-version: ${{ matrix.ruby }}
+          apt-get: "haveged libyaml-dev cmake g++"
+
+      - name: Build capstone 5 from source
+        run: |
+          git clone --depth 1 --branch 5.0.7 https://github.com/capstone-engine/capstone.git /tmp/capstone
+          cd /tmp/capstone
+          cmake -B build -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -DBUILD_SHARED_LIBS=ON
+          cmake --build build -j$(nproc)
+          sudo cmake --install build
+          sudo ldconfig
+
+      - name: Install dependencies
+        run: bundle install --jobs 4 --retry 3
+
+      - name: Publish to RubyGems
+        uses: rubygems/release-gem@v1
+
+      - name: Create GitHub release
+        run: |
+          tag_name="$(git describe --tags --abbrev=0)"
+          gh release create "${tag_name}" --verify-tag --generate-notes
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

data/Rakefile

@@ -2,6 +2,8 @@ ENV["MT_NO_PLUGINS"] = "1"
 
 require "rake/testtask"
 require "rake/clean"
+require "bundler"
+Bundler::GemHelper.install_tasks
 
 XML_FILE  = "tmp/onebigfile.xml"
 ISA_FILE  = "tmp/ISA_A64_xml_v88A-2021-12.tar.gz"
@@ -160,12 +162,6 @@ file SYSTEM_REGS_FILE do |t|
   download SYSTEM_REGS_URL, t.name
 end
 
-rule ".tab.rb" => [".y"] do |t|
-  puts "#" * 90
-  sh "gel exec racc -v #{t.source}"
-  puts "#" * 90
-end
-
 Rake::TestTask.new(:test) do |t|
   t.libs << "test/lib" << "test"
   t.test_files = FileList['test/**/*_test.rb']
@@ -173,8 +169,6 @@ Rake::TestTask.new(:test) do |t|
   t.warning = true
 end
 
-task :test => "lib/aarch64/parser.tab.rb"
-
 task :default => :test
 
 task "autotest" do

data/aarch64.gemspec

@@ -14,7 +14,6 @@ Gem::Specification.new do |s|
   s.homepage    = "https://github.com/tenderlove/aarch64"
   s.license     = "Apache-2.0"
 
-  s.add_runtime_dependency 'racc', '~> 1.6'
   s.add_development_dependency 'hatstone', '~> 1.0.0'
   s.add_development_dependency 'jit_buffer', '~> 1.0.0'
   s.add_development_dependency 'minitest', '~> 5.15'

data/lib/aarch64/instructions/add/addsub_ext.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module ADD
+      # ADD (extended register) -- A64
+      # Add (extended register)
+      # ADD  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+      # ADD  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
+      class ADDSUB_ext < Instruction
+        def initialize rd, rn, rm, extend, amount, sf
+          @rd     = check_mask(rd, 0x1f)
+          @rn     = check_mask(rn, 0x1f)
+          @rm     = check_mask(rm, 0x1f)
+          @extend = check_mask(extend, 0x07)
+          @amount = check_mask(amount, 0x07)
+          @sf     = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ADD_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
+        end
+
+        private
+
+        def ADD_addsub_ext sf, rm, option, imm3, rn, rd
+          insn = 0b0_0_0_01011_00_1_00000_000_000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((rm) << 16)
+          insn |= ((option) << 13)
+          insn |= ((imm3) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/add/addsub_imm.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    module ADD
+      # ADD (immediate) -- A64
+      # Add (immediate)
+      # ADD  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
+      class ADDSUB_imm < Instruction
+        def initialize rd, rn, imm12, sh, sf
+          @rd    = check_mask(rd, 0x1f)
+          @rn    = check_mask(rn, 0x1f)
+          @imm12 = check_mask(imm12, 0xfff)
+          @sh    = check_mask(sh, 0x01)
+          @sf    = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ADD_addsub_imm(@sf, @sh, @imm12, @rn, @rd)
+        end
+
+        private
+
+        def ADD_addsub_imm sf, sh, imm12, rn, rd
+          insn = 0b0_0_0_100010_0_000000000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((sh) << 22)
+          insn |= ((imm12) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/add/addsub_shift.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module ADD
+      # ADD (shifted register) -- A64
+      # Add (shifted register)
+      # ADD  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+      # ADD  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+      class ADDSUB_shift < Instruction
+        def initialize xd, xn, xm, shift, amount, sf
+          @xd     = check_mask(xd, 0x1f)
+          @xn     = check_mask(xn, 0x1f)
+          @xm     = check_mask(xm, 0x1f)
+          @shift  = check_mask(shift, 0x03)
+          @amount = check_mask(amount, 0x3f)
+          @sf     = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ADD_addsub_shift(@sf, @shift, @xm, @amount, @xn, @xd)
+        end
+
+        private
+
+        def ADD_addsub_shift sf, shift, rm, imm6, rn, rd
+          insn = 0b0_0_0_01011_00_0_00000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((shift) << 22)
+          insn |= ((rm) << 16)
+          insn |= ((imm6) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/add.rb

@@ -0,0 +1,9 @@
+module AArch64
+  module Instructions
+    module ADD
+      autoload :ADDSUB_ext, "aarch64/instructions/add/addsub_ext"
+      autoload :ADDSUB_imm, "aarch64/instructions/add/addsub_imm"
+      autoload :ADDSUB_shift, "aarch64/instructions/add/addsub_shift"
+    end
+  end
+end

data/lib/aarch64/instructions/adds/addsub_ext.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module ADDS
+      # ADDS (extended register) -- A64
+      # Add (extended register), setting flags
+      # ADDS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+      # ADDS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
+      class ADDSUB_ext < Instruction
+        def initialize d, n, m, extend, amount, sf
+          @d      = check_mask(d, 0x1f)
+          @n      = check_mask(n, 0x1f)
+          @m      = check_mask(m, 0x1f)
+          @extend = check_mask(extend, 0x07)
+          @amount = check_mask(amount, 0x07)
+          @sf     = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ADDS_addsub_ext(@sf, @m, @extend, @amount, @n, @d)
+        end
+
+        private
+
+        def ADDS_addsub_ext sf, rm, option, imm3, rn, rd
+          insn = 0b0_0_1_01011_00_1_00000_000_000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((rm) << 16)
+          insn |= ((option) << 13)
+          insn |= ((imm3) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adds/addsub_imm.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    module ADDS
+      # ADDS (immediate) -- A64
+      # Add (immediate), setting flags
+      # ADDS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
+      # ADDS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
+      class ADDSUB_imm < Instruction
+        def initialize d, n, imm, shift, sf
+          @d     = check_mask(d, 0x1f)
+          @n     = check_mask(n, 0x1f)
+          @imm   = check_mask(imm, 0xfff)
+          @shift = check_mask(shift, 0x01)
+          @sf    = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ADDS_addsub_imm(@sf, @shift, @imm, @n, @d)
+        end
+
+        private
+
+        def ADDS_addsub_imm sf, sh, imm12, rn, rd
+          insn = 0b0_0_1_100010_0_000000000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((sh) << 22)
+          insn |= ((imm12) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adds/addsub_shift.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module ADDS
+      # ADDS (shifted register) -- A64
+      # Add (shifted register), setting flags
+      # ADDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+      # ADDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+      class ADDSUB_shift < Instruction
+        def initialize xd, xn, xm, shift, amount, sf
+          @xd     = check_mask(xd, 0x1f)
+          @xn     = check_mask(xn, 0x1f)
+          @xm     = check_mask(xm, 0x1f)
+          @shift  = check_mask(shift, 0x03)
+          @amount = check_mask(amount, 0x3f)
+          @sf     = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ADDS_addsub_shift(@sf, @shift, @xm, @amount, @xn, @xd)
+        end
+
+        private
+
+        def ADDS_addsub_shift sf, shift, rm, imm6, rn, rd
+          insn = 0b0_0_1_01011_00_0_00000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((shift) << 22)
+          insn |= ((rm) << 16)
+          insn |= ((imm6) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adds.rb

@@ -0,0 +1,9 @@
+module AArch64
+  module Instructions
+    module ADDS
+      autoload :ADDSUB_ext, "aarch64/instructions/adds/addsub_ext"
+      autoload :ADDSUB_imm, "aarch64/instructions/adds/addsub_imm"
+      autoload :ADDSUB_shift, "aarch64/instructions/adds/addsub_shift"
+    end
+  end
+end

data/lib/aarch64/instructions/and/log_imm.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module AND
+      # AND (immediate) -- A64
+      # Bitwise AND (immediate)
+      # AND  <Wd|WSP>, <Wn>, #<imm>
+      # AND  <Xd|SP>, <Xn>, #<imm>
+      class LOG_imm < Instruction
+        def initialize rd, rn, immr, imms, n, sf
+          @rd   = check_mask(rd, 0x1f)
+          @rn   = check_mask(rn, 0x1f)
+          @immr = check_mask(immr, 0x3f)
+          @imms = check_mask(imms, 0x3f)
+          @n    = check_mask(n, 0x01)
+          @sf   = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          AND_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
+        end
+
+        private
+
+        def AND_log_imm sf, n, immr, imms, rn, rd
+          insn = 0b0_00_100100_0_000000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((n) << 22)
+          insn |= ((immr) << 16)
+          insn |= ((imms) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/and/log_shift.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module AND
+      # AND (shifted register) -- A64
+      # Bitwise AND (shifted register)
+      # AND  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+      # AND  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+      class LOG_shift < Instruction
+        def initialize xd, xn, xm, shift, amount, sf
+          @xd     = check_mask(xd, 0x1f)
+          @xn     = check_mask(xn, 0x1f)
+          @xm     = check_mask(xm, 0x1f)
+          @shift  = check_mask(shift, 0x03)
+          @amount = check_mask(amount, 0x3f)
+          @sf     = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          AND_log_shift(@sf, @shift, @xm, @amount, @xn, @xd)
+        end
+
+        private
+
+        def AND_log_shift sf, shift, rm, imm6, rn, rd
+          insn = 0b0_00_01010_00_0_00000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((shift) << 22)
+          insn |= ((rm) << 16)
+          insn |= ((imm6) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/and.rb

@@ -0,0 +1,8 @@
+module AArch64
+  module Instructions
+    module AND
+      autoload :LOG_imm, "aarch64/instructions/and/log_imm"
+      autoload :LOG_shift, "aarch64/instructions/and/log_shift"
+    end
+  end
+end

data/lib/aarch64/instructions/ands/log_imm.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module ANDS
+      # ANDS (immediate) -- A64
+      # Bitwise AND (immediate), setting flags
+      # ANDS  <Wd>, <Wn>, #<imm>
+      # ANDS  <Xd>, <Xn>, #<imm>
+      class LOG_imm < Instruction
+        def initialize rd, rn, immr, imms, n, sf
+          @rd   = check_mask(rd, 0x1f)
+          @rn   = check_mask(rn, 0x1f)
+          @immr = check_mask(immr, 0x3f)
+          @imms = check_mask(imms, 0x3f)
+          @n    = check_mask(n, 0x01)
+          @sf   = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ANDS_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
+        end
+
+        private
+
+        def ANDS_log_imm sf, n, immr, imms, rn, rd
+          insn = 0b0_11_100100_0_000000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((n) << 22)
+          insn |= ((immr) << 16)
+          insn |= ((imms) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ands/log_shift.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module ANDS
+      # ANDS (shifted register) -- A64
+      # Bitwise AND (shifted register), setting flags
+      # ANDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+      # ANDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+      class LOG_shift < Instruction
+        def initialize xd, xn, xm, shift, amount, sf
+          @xd     = check_mask(xd, 0x1f)
+          @xn     = check_mask(xn, 0x1f)
+          @xm     = check_mask(xm, 0x1f)
+          @shift  = check_mask(shift, 0x03)
+          @amount = check_mask(amount, 0x3f)
+          @sf     = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          ANDS_log_shift(@sf, @shift, @xm, @amount, @xn, @xd)
+        end
+
+        private
+
+        def ANDS_log_shift sf, shift, rm, imm6, rn, rd
+          insn = 0b0_11_01010_00_0_00000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((shift) << 22)
+          insn |= ((rm) << 16)
+          insn |= ((imm6) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ands.rb

@@ -0,0 +1,8 @@
+module AArch64
+  module Instructions
+    module ANDS
+      autoload :LOG_imm, "aarch64/instructions/ands/log_imm"
+      autoload :LOG_shift, "aarch64/instructions/ands/log_shift"
+    end
+  end
+end

data/lib/aarch64/instructions/eor/log_imm.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module EOR
+      # EOR (immediate) -- A64
+      # Bitwise Exclusive OR (immediate)
+      # EOR  <Wd|WSP>, <Wn>, #<imm>
+      # EOR  <Xd|SP>, <Xn>, #<imm>
+      class LOG_imm < Instruction
+        def initialize rd, rn, immr, imms, n, sf
+          @rd   = check_mask(rd, 0x1f)
+          @rn   = check_mask(rn, 0x1f)
+          @n    = check_mask(n, 0x01)
+          @immr = check_mask(immr, 0x3f)
+          @imms = check_mask(imms, 0x3f)
+          @sf   = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          EOR_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
+        end
+
+        private
+
+        def EOR_log_imm sf, n, immr, imms, rn, rd
+          insn = 0b0_10_100100_0_000000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((n) << 22)
+          insn |= ((immr) << 16)
+          insn |= ((imms) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/eor/log_shift.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    module EOR
+      # EOR (shifted register) -- A64
+      # Bitwise Exclusive OR (shifted register)
+      # EOR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+      # EOR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+      class LOG_shift < Instruction
+        def initialize rd, rn, rm, shift, imm6, sf
+          @rd    = check_mask(rd, 0x1f)
+          @rn    = check_mask(rn, 0x1f)
+          @rm    = check_mask(rm, 0x1f)
+          @shift = check_mask(shift, 0x03)
+          @imm6  = check_mask(imm6, 0x3f)
+          @sf    = check_mask(sf, 0x01)
+        end
+
+        def encode _
+          EOR_log_shift(@sf, @shift, @rm, @imm6, @rn, @rd)
+        end
+
+        private
+
+        def EOR_log_shift sf, shift, rm, imm6, rn, rd
+          insn = 0b0_10_01010_00_0_00000_000000_00000_00000
+          insn |= ((sf) << 31)
+          insn |= ((shift) << 22)
+          insn |= ((rm) << 16)
+          insn |= ((imm6) << 10)
+          insn |= ((rn) << 5)
+          insn |= (rd)
+          insn
+        end
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/eor.rb

@@ -0,0 +1,8 @@
+module AArch64
+  module Instructions
+    module EOR
+      autoload :LOG_imm, "aarch64/instructions/eor/log_imm"
+      autoload :LOG_shift, "aarch64/instructions/eor/log_shift"
+    end
+  end
+end