HDLRuby 3.7.9 → 3.8.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -17,6 +17,15 @@ hdrcc --get-tuto
 
 __What's new_
 
+For HDLRuby version 3.8.0:
+
+* Added parallel enumerators (e.g., heach): can iterate like Ruby for describing parallel hardware.
+
+* Added metaprogramming through standard HDLRuby constructs (e.g., hif): no need to use Ruby code any longer.
+
+* Fixed compile bugs for windows.
+
+
 For HDLRuby version 3.7.9:
 
 * Added Python code generation from the software sequencers.

data/ext/hruby_sim/hruby_rcsim_build.c

@@ -280,7 +280,8 @@ VALUE rcsim_make_behavior(VALUE mod, VALUE timed) {
         register_init_behavior(behavior);
     }
     behavior->active_time = 0;
-    behavior->thread = NULL;
+    // behavior->thread = NULL;
+    behavior->thread = 0;
     /* Returns the C behavior embedded into a ruby VALUE. */
     VALUE res;
     rcsim_to_value(BehaviorS,behavior,res);
@@ -466,7 +467,8 @@ VALUE rcsim_load_c(VALUE mod, VALUE codeV, VALUE libnameV, VALUE funcnameV) {
         fprintf(stderr,"LoadLibrary failed with error code %ld\n", dwError);
         exit(-1);
     }
-    code->function = GetProcAddress(handle,funcname);
+    // code->function = GetProcAddress(handle,funcname);
+    code->function = (void (*)(Code))GetProcAddress(handle,funcname);
     if (code->function == NULL) {
         fprintf(stderr,"Unable to get function: %s\n",code->name);
         exit(-1);

data/ext/hruby_sim/hruby_sim_tree_calc.c

@@ -191,7 +191,7 @@ void calc_ref_rangeS(Reference ref, long long* first, long long *last,
         Cast refc = (Cast)ref;
         /* Compute the range for the child. */
         long long cfirst, clast;
-        calc_ref_rangeS(refc->child,&cfirst,&clast,sig);
+        calc_ref_rangeS((Reference)(refc->child),&cfirst,&clast,sig);
         /* Update first and last using the cast. */
         /* Both first and last should be equal since the type of the cast sets
          * the width */

data/ext/hruby_sim/hruby_sim_vcd.c

@@ -207,6 +207,76 @@ static void vcd_print_signal_cvalue(SignalI signal) {
 }
 
 
+/** Checks if a statement contains any declaration.
+ *  @param stmnt the statement to check. */
+static int vcd_statement_has_decl(Statement stmnt) {
+    // printf("stmnt kind=%d\n",stmnt->kind);
+    switch(stmnt->kind) {
+        case TRANSMIT: 
+        case PRINT:
+            /* No declaration. */
+            return 0;
+        case HIF:
+            {
+                HIf hif = (HIf)stmnt;
+                /* Recruse on the sub statements of the if.*/
+                if (vcd_statement_has_decl(hif->yes)) return 1;
+                for(int i=0; i<hif->num_noifs; ++i)
+                    if (vcd_statement_has_decl(hif->nostmnts[i])) 
+                        return 1;
+                if (hif->no)
+                    return vcd_statement_has_decl(hif->no);
+                /* No declaration. */
+                return 0;
+            }
+        case HCASE:
+            {
+                HCase hcase = (HCase)stmnt;
+                /* Recruse on the sub statements of the case.*/
+                for(int i=0; i<hcase->num_whens; ++i)
+                    if (vcd_statement_has_decl(hcase->stmnts[i]))
+                        return 1;
+                if (hcase->defolt)
+                    return vcd_statement_has_decl(hcase->defolt);
+                /* No declaration. */
+                return 0;
+            }
+        case TIME_WAIT:
+            /* No declaration. */
+            return 0;
+        case TIME_REPEAT:
+            {
+                TimeRepeat rep = (TimeRepeat)stmnt;
+                /* Recruse on the sub statements of the repeat.*/
+                for(long long i=0; i<rep->number; ++i)
+                    if (vcd_statement_has_decl(rep->statement))
+                        return 1;
+                /* No declaration. */
+                return 0;
+            }
+        case TIME_TERMINATE:
+            /* No declaration. */
+            return 0;
+        case BLOCK:
+            {
+                Block blk = (Block)stmnt;
+                if (blk->num_inners != 0) return 1;
+                /* Recruse on the sub statements. */
+                for(int i=0; i<blk->num_stmnts; ++i)
+                    if (vcd_statement_has_decl(blk->stmnts[i]))
+                        return 1;
+                /* No declaration. */
+                return 0;
+            }
+        default:
+            perror("Invalid kind for a statement."); 
+    }
+    /* Should not be here though. */
+    return 0;
+}
+
+
+
 /** Prints the hierarchy content of a system type.
  *  @param system the system to print. */
 static void vcd_print_systemT_content(SystemT system);
@@ -215,13 +285,74 @@ static void vcd_print_systemT_content(SystemT system);
  *  @param scope the scope to print. */
 static void vcd_print_scope(Scope scope);
 
+/** Prints the hierarchy of a block.
+ *  @param block the block to print. */
+static void vcd_print_block(Block block);
+
+/** Prints the hierarchy of a statement.
+ *  @param stmnt the statement to print. */
+static void vcd_print_statement(Statement stmnt) {
+    // printf("stmnt kind=%d\n",stmnt->kind);
+    switch(stmnt->kind) {
+        case TRANSMIT: 
+        case PRINT:
+            /* Nothing to do. */
+            break;
+        case HIF:
+            {
+                HIf hif = (HIf)stmnt;
+                /* Recruse on the sub statements of the if.*/
+                vcd_print_statement(hif->yes);
+                for(int i=0; i<hif->num_noifs; ++i)
+                    vcd_print_statement(hif->nostmnts[i]);
+                if (hif->no)
+                    vcd_print_statement(hif->no);
+                break;
+            }
+        case HCASE:
+            {
+                HCase hcase = (HCase)stmnt;
+                /* Recruse on the sub statements of the case.*/
+                for(int i=0; i<hcase->num_whens; ++i)
+                    vcd_print_statement(hcase->stmnts[i]);
+                if (hcase->defolt)
+                    vcd_print_statement(hcase->defolt);
+                break;
+            }
+        case TIME_WAIT:
+            /* Nothing to do. */
+            break;
+        case TIME_REPEAT:
+            {
+                TimeRepeat rep = (TimeRepeat)stmnt;
+                /* Recruse on the sub statements of the repeat.*/
+                for(long long i=0; i<rep->number; ++i)
+                    vcd_print_statement(rep->statement);
+                break;
+            }
+        case TIME_TERMINATE:
+            /* Nothing to do. */
+            break;
+        case BLOCK:
+            {
+                /* Block case: there is a specific function for it. */
+                vcd_print_block((Block)stmnt);
+                break;
+            }
+        default:
+            perror("Invalid kind for a statement."); 
+    }
+}
+
 
 /** Prints the hierarchy of a block.
  *  @param block the block to print. */
 static void vcd_print_block(Block block) {
     int i;
+    // printf("vcd_print_block\n");
     /* Do not print block with no declaration. */
-    if (block->num_inners == 0) return;
+    // if (block->num_inners == 0) return;
+    if (!vcd_statement_has_decl(block)) return;
 
     /* Declares the block if named. */
     vcd_print("$scope module ");
@@ -233,6 +364,11 @@ static void vcd_print_block(Block block) {
         vcd_print_var(block->inners[i]);
     }
 
+    /* Recurse on the statements if any. */
+    for(i=0; i<block->num_stmnts; ++i) {
+        vcd_print_statement(block->stmnts[i]);
+    }
+
     /* Close the hierarchy. */
     vcd_print("$upscope $end\n");
 }
@@ -258,6 +394,7 @@ static void vcd_print_systemI(SystemI systemI) {
  *  @param scope the scope to print the inside. */
 static void vcd_print_scope_content(Scope scope) {
     int i;
+    // printf("vcd_print_scope_content\n");
 
     /* Declare the inners of the systems. */
     for(i=0; i<scope->num_inners; ++i) {

data/lib/HDLRuby/hdr_samples/invalid_function.rb

@@ -0,0 +1,26 @@
+# Sample for testing an invalid function: should generate an error.
+
+
+hdef :func do |val|
+  [8].inner :res
+  hif (val == 1) { res <= _h60 }
+  helse          { res <= _h70 }
+end
+
+
+system :with_func do
+    [8].inner :val,:res
+
+    res <= func(val)
+
+    timed do
+        val <= 0
+        !10.ns
+        val <= 1
+        !10.ns
+        val <= 2
+        !10.ns
+        val <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_henumerable.rb

@@ -7,7 +7,7 @@ include HDLRuby::High::Std
 # - The second check is for hany?
 # - The third check is for hchain
 # - The forth check is for hmap
-# - The fifth check is for hmap with with_index
+# - The fifth check is for hmap with hwith_index
 # - The sixth check is for hcompact
 # - The seventh checks is for hcount
 # - The eighth check is for hcycle
@@ -35,6 +35,8 @@ include HDLRuby::High::Std
 # - The thirtieth check is for suniq
 # - The thirty first check is for hzip
 #
+# - The remaing checks the enumerators apply on values directly.
+#
  
 system :henmerable_checks do
 
@@ -89,11 +91,11 @@ system :henmerable_checks do
 
     bit[8][-8].inner :res14, :res15
 
-    res14 <= vals.hmap.with_index { |val,i| val + i }
+    res14 <= vals.hmap.hwith_index { |val,i| val + i }
 
     par(clk.posedge) do
       # hprint("&0\n");
-      res15 <= vals.hmap.with_index { |val,i| val + i }
+      res15 <= vals.hmap.hwith_index { |val,i| val + i }
     end
 
     bit[8][-8].inner vals2: [ _h00, _h10, _h00, _h0B, _hFE, _h00, _h5C, _h00 ]
@@ -147,14 +149,14 @@ system :henmerable_checks do
 
     par(clk.posedge) do
       # hprint("*0\n")
-      vals.heach_cons(3).with_index { |(a,b,c),i| res27[i] <= a+b+c }
+      vals.heach_cons(3).hwith_index { |(a,b,c),i| res27[i] <= a+b+c }
     end
 
     bit[8][-8].inner :res28
     
     par(clk.posedge) do
       # hprint("/0\n")
-      vals.heach_slice(3).with_index do |(a,b,c),i| 
+      vals.heach_slice(3).hwith_index do |(a,b,c),i| 
         if c then
           res28[i] <= a+b+c
         elsif b then
@@ -204,7 +206,7 @@ system :henmerable_checks do
 
     par(clk.posedge) do
       # hprint(":0\n")
-      res36 <= vals.hinject(:+)
+      res36 <= vals.(:+)
     end
 
     [8].inner :res37
@@ -284,7 +286,7 @@ system :henmerable_checks do
 
     par(clk.posedge) do
         # hprint("_0\n")
-      (5..10).hreverse_each.with_index { |val,i| res52[i] <= val }
+      (5..10).hreverse_each.hwith_index { |val,i| res52[i] <= val }
     end
 
     bit[8][-10].inner :res53X, :res54X
@@ -325,10 +327,10 @@ system :henmerable_checks do
 
     # res59 <= vals3.huniq
 
-    # par(clk.posedge) do
-    #   # hprint("~0\n")
-    #   res60 <= vals.huniq { |val| val & _h0F }
-    # end
+    # # par(clk.posedge) do
+    # #   # hprint("~0\n")
+    # #   res60 <= vals.huniq { |val| val & _h0F }
+    # # end
 
     bit[8][-8].inner :res61
     bit[8][-8].inner :res62
@@ -340,6 +342,28 @@ system :henmerable_checks do
       vals.hzip([_h12]*8).each_with_index { |(a,b),i| res62[i] <= a+b }
     end
 
+    # Test enumerators of values.
+    inner :res63, :res64, :res65
+
+    res63 <= _b0101011.(:|)
+    res64 <= _b0101011.(:^)
+    res65 <= _b0101011.(:&)
+
+    [8].inner :res66
+
+    res66 <= [_h01, _h02, _h03, _h04].(:+)
+
+
+    # Test signal declarations within iterator block.
+    vals.heach do |v,i|
+      inner :sig
+      sig <= v[0]
+    end
+
+    [_h0001, _h0002, _h0003].heach.hwith_index do |v,i|
+      [16].inner :sig
+      sig <= v + i
+    end
 
 
 

data/lib/HDLRuby/hdr_samples/with_val_control.rb

@@ -0,0 +1,107 @@
+
+
+# A benchmark for testing hif with value condition: the sould produce
+# meta programming.
+system :with_seq_if_bench do
+    inner :clk
+    [2].inner :s
+    [8].inner :x,:y, :z
+    [8].inner :u,:v, :w
+    [8].inner :a, :b
+
+    hif(9) do
+      puts "hif(9)"
+      [8].inner q: 6
+      seq do
+        hif(s==2) { x <= 1 }
+      end
+    end
+    helse do
+      [8].inner r: 6
+      puts "hif(9) helse"
+      seq do
+        hif(s==1) { x <= 2 }
+      end
+    end
+
+    hif(0) do
+      puts "hif(0)"
+      [8].inner q: 7
+      seq do
+        hif(s==2) { y <= 1 }
+      end
+    end
+    helse do
+      [8].inner r: 7
+      puts "hif(0) helse"
+      seq do
+        hif(s==1) { y <= 2 }
+      end
+    end
+
+    hif(0) do
+      puts "hif(0)"
+      [8].inner q: 9
+      z <= 0
+    end
+    helsif(2) do
+      puts "hif(0) helsif(2)"
+      [8].inner r: 9
+      z <= 4
+    end
+    helse do
+      puts "hif(0) helsif(2) helse"
+      [8].inner t: 9
+      z <= 5
+    end
+
+    hcase(2)
+    hwhen(0) { puts "hcase(2) hwhen(0)"; [8].inner(q: 13); u <= 0 }
+    hwhen(1) { puts "hcase(2) hwhen(1)"; [8].inner(q: 14); u <= 1 }
+    hwhen(2) { puts "hcase(2) hwhen(2)"; [8].inner(q: 15); u <= 2 }
+    helse    { puts "hcase(2) helse"   ; [8].inner(q: 16); u <= 3 }
+
+    hcase(4)
+    hwhen(0) { puts "hcase(4) hwhen(0)"; [8].inner(r: 13); v <= 0 }
+    hwhen(1) { puts "hcase(4) hwhen(1)"; [8].inner(r: 14); v <= 1 }
+    hwhen(2) { puts "hcase(4) hwhen(2)"; [8].inner(r: 15); v <= 2 }
+    helse    { puts "hcase(4) helse"   ; [8].inner(r: 16); v <= 3 }
+
+    seq(clk.posedge) do
+      hif(6) do
+        [8].inner q: 20
+        puts "hif(6)"
+        w <= w + 1
+      end
+    end
+
+    seq(mux(1,s,clk.posedge)) do
+      a <= a + 1
+    end
+
+    seq(mux(0,s,clk.posedge)) do
+      b <= b + 1
+    end
+
+        
+
+    timed do
+      clk <= 0
+      w   <= 0
+      a   <= 0
+      b   <= 0
+      !10.ns
+      clk <= ~clk
+      s <= 0
+      !10.ns
+      clk <= ~clk
+      s <= 1
+      !10.ns
+      clk <= ~clk
+      s <= 2
+      !10.ns
+      clk <= ~clk
+      s <= 3
+      !10.ns
+    end
+end

data/lib/HDLRuby/hdrcc.rb

@@ -549,12 +549,23 @@ $optparse = OptionParser.new do |opts|
 end
 $optparse.parse!
 
-# show? "options=#{$options}"
+# puts "options=#{$options}"
 
 # Check the compatibility of the options
-if $options.count {|op| [:yaml,:hdr,:verilog,:vhdl,:svg].include?(op) } > 1 then
-    warn("Please choose either YAML, HDLRuby, Verilog HDL, VHDL, SVG (visualize) output.")
-    puts $optparse.help()
+if $options.count {|op,val| [:yaml,:hdr,:verilog,:vhdl,:svg].include?(op) } > 1 then
+    warn("**Warning**: please choose either YAML, HDLRuby, Verilog HDL, VHDL, SVG (visualize) output.")
+    # puts $optparse.help()
+    exit
+end
+if $options.count {|op,val| [:rcsim, :csim, :rsim].include?(op) } > 1 then
+    warn("**Warning**: please choose either RCSIM, CSIM or RSIM simulator.")
+    # puts $optparse.help()
+    exit
+end
+if $options.count {|op,val| [:yaml,:hdr,:verilog,:vhdl,:svg,:rcsim,:csim,:rsim].include?(op) } > 1 then
+    warn("**Warning**: please choose either simulation or code generation.")
+    # puts $optparse.help()
+    exit
 end
 
 # Get the the input and the output files.