HDLRuby 3.3.4 → 3.4.0

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data/README.md

@@ -17,6 +17,19 @@ hdrcc --get-tuto
 
 __What's new__
 
+For HDLRuby version 3.4.0:
+
+ * Improved synchronization of the browser-base graphical interface with the HDLRuby simulator.
+
+ * Added a Verilog HDL parsing library for Ruby. This library will be released separately once it is fully stabilized."
+
+ * Added a HDLRuby generating library from the a Verilog HDL AST provided by the above-mentioned library.
+
+ * Added a standalone tool for converting Verilog HDL files to HDLRuby called [v2hdr](#converting-verilog-hdl-to-hdlruby). This tool is still experimental though.
+
+ * Added a HDLRuby command for [loading a Verilog HDL file from a HDLRuby description](#loading-verilog-hdl-from-hdlruby).
+
+
 For HDLRuby version 3.3.0:
  
  * Remade the description of software components using the program construct.
@@ -3929,6 +3942,57 @@ The naming convention of the samples is the following:
 * `<name>_bench.rb`: sample including a simulation benchmark, these are the only samples that can be simulated using `hdrcc -S`. Please notice that such a sample cannot be converted to VHDL or Verilog HDL yet.
 * `with_<name>.rb`: sample illustrating a single aspect of HDLRuby or one of its libraries, usually includes a benchmark.
 
+# Converting Verilog HDL to HDLRuby
+
+While the HDLRuby framwork does not support Verilog HDL files as input yet, a standalone tool is provided for converting those files to HDLRuby. For that please use the following command:
+
+```bash
+v2hdr <input Verilog HDL file> <output HDLRuby file>
+```
+
+For example, assuming that you have a Verilog ddHDL named 'adder.v' describing and adder circuit, you can convert it to HDLRuby as follows:
+
+```bash
+v2hdr adder.v adder.v.rb
+```
+
+Another possibility is to directly load the Verilog HDL file from a HDLRuby description using the command `require_verilog`.
+For example, assuming `adder.v` contains the following code:
+
+```verilog
+module adder(x,y,z);
+  input[7:0] x,y;
+  output[7:0] z;
+  
+  assign z = x + y;
+endmodule
+```
+
+It can be loaded the be instantiated like any other module in HDLRuby as follows:
+
+```ruby
+require_verilog "adder.v"
+
+system :my_IC do
+   [8].inner :a, :b, :c
+
+   adder(:my_adder).(a,b,c)
+
+   ...
+end
+```
+
+
+__Notes__:
+
+* Verilog HDL accepts signal and module names in any letter case, while HDLRuby reserves identifiers starting with a capital letter for constants. To avoid conflicts, Verilog HDL names that begin with a capital letter are prefixed with an underscore (`_`) in HDLRuby. For example, if the Verilog HDL module name in the previous example were `ADDER`, it would be renamed to `_ADDER` in HDLRuby. Instantiating such a module would be done as follows:
+
+  ```ruby
+  _ADDER(:my_add).(a,b,c)
+  ```
+
+* With the current version of HDLRuby, the Verilog HDL files are first converted to HDLRuby before being loaded using the standalone `v2hdr` tool.
+
 
 # Contributing
 
@@ -3938,7 +4002,6 @@ Bug reports and pull requests are welcome on GitHub at https://github.com/civol/
 # To do
 
  * Find and fix the (maybe) terrifying number of bugs.
- * Add a GUI (any volunteer to do it?).
 
 
 # License

data/exe/v2hdr

@@ -0,0 +1,3 @@
+#!/usr/bin/ruby
+
+require 'HDLRuby/v2hdr.rb'

data/ext/hruby_sim/hruby_rcsim_build.c

@@ -554,6 +554,7 @@ VALUE rcsim_make_timeWait(VALUE mod, VALUE unitV, VALUE delayV) {
     /* Adjust the delay depending on the unit. */
     const char* unit = rb_id2name(SYM2ID(unitV));
     switch(unit[0]) {
+        case 'f': delay /= 1000;          break;
         case 'p': /* Ok as is. */         break;
         case 'n': delay *= 1000;          break;
         case 'u': delay *= 1000000;       break;

data/lib/HDLRuby/hdr_samples/adder8.v

@@ -0,0 +1,6 @@
+module adder8(x,y,z);
+  input[7:0] x,y;
+  output[7:0] z;
+  
+  assign z = x + y;
+endmodule

data/lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb

@@ -1,3 +1,5 @@
+raise "Deprecated code."
+
 # require "../hruby_low2c.rb"
 
 # An 8-bit register with C encrypting.

data/lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb

@@ -1,3 +1,5 @@
+raise "Deprecated code."
+
 require 'HDLRuby/backend/allocator'
 require 'HDLRuby/hdr_samples/mei8'
 

data/lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb

@@ -1,3 +1,5 @@
+raise "Deprecated code."
+
 require 'HDLRuby/backend/allocator'
 
 ## A generic CPU description

data/lib/HDLRuby/hdr_samples/verilog_parser_bench.rb

@@ -0,0 +1,36 @@
+$LOAD_PATH << "#{__dir__}/../../"
+
+require "HDLRuby/verilog_hruby.rb"
+
+parser = VerilogTools::Parser.new
+
+ast = nil
+
+begin
+  ast = parser.run(filename: ARGV[0], compress: ARGV[1] == "--compress" )
+rescue => error
+  puts error
+  exit
+end
+
+puts "#################################"
+puts "##             AST             ##"
+puts "#################################"
+puts "\n"
+
+puts ast
+
+hdlruby = ""
+begin
+  hdlruby = ast.to_HDLRuby
+rescue => error
+  puts error
+  exit
+end
+
+puts "\n"
+puts "#################################"
+puts "##           HDLRuby           ##"
+puts "#################################"
+
+puts hdlruby

data/lib/HDLRuby/hdr_samples/with_handshake.rb

@@ -1,3 +1,5 @@
+raise "Deprecated code."
+
 require 'std/handshakes.rb'
 
 include HDLRuby::High::Std

data/lib/HDLRuby/hdr_samples/with_memory.rb

@@ -1,3 +1,5 @@
+raise "Deprecated code."
+
 require 'std/memory.rb'
 
 include HDLRuby::High::Std

data/lib/HDLRuby/hdr_samples/with_nand_board.rb

@@ -11,7 +11,7 @@ system :nand_board do
     inner :clk
     # Description of the board.
     # It is updated at each rising edge of +clk+.
-    board(:nand,8080) do
+    board(:nand,http_port: 8080) do
         actport clk.posedge
         sw din0: din0
         sw din1: din1

data/lib/HDLRuby/hdr_samples/with_reconf.rb

@@ -1,3 +1,4 @@
+raise "Deprecated code."
 
 # Some system that can be used for reconfiguration.
 system :sys0 do

data/lib/HDLRuby/hdr_samples/with_verilog.rb

@@ -0,0 +1,24 @@
+# Sample HDLRuby instantiating a Verilog HDL-described adder (adder.v)
+
+require_verilog "adder8.v"
+
+system :verilog_bench do
+  [8].inner :a, :b, :c
+
+  # Instantiate the adder.
+  adder8(:my_adder8).(a,b,c)
+
+  # Testing it.
+  timed do
+    a <= 0
+    b <= 0
+    repeat(100) do
+      repeat(100) do
+        !10.ns
+        b <= b + 1
+      end
+      a <= a + 1
+    end
+    !10.ns
+  end
+end

data/lib/HDLRuby/hruby_high.rb

@@ -1235,8 +1235,10 @@ module HDLRuby::High
         end
 
         # Declares a high-level sequential behavior activated on a list of
-        # +events+, and built by executing +ruby_block+.
-        def seq(*events, &ruby_block)
+        # +events+, with possible name +name+ and built by executing
+        # +ruby_block+.
+        # def seq(*events, &ruby_block)
+        def seq(*events, name: nil, &ruby_block)
             # Ensure there is a block.
             ruby_block = proc {} unless block_given?
             # Preprocess the events.
@@ -1244,12 +1246,16 @@ module HDLRuby::High
                 event.respond_to?(:to_event) ? event.to_event : event
             end
             # Create and add the resulting behavior.
-            self.add_behavior(Behavior.new(:seq,*events,&ruby_block))
+            # self.add_behavior(Behavior.new(:seq,*events,&ruby_block))
+            self.add_behavior(Behavior.new(:seq,*events,name: name,
+                                           &ruby_block))
         end
 
         # Declares a high-level parallel behavior activated on a list of
-        # +events+, and built by executing +ruby_block+.
-        def par(*events, &ruby_block)
+        # +events+, with possible name +name+ and built by executing
+        # +ruby_block+.
+        # def par(*events, &ruby_block)
+        def par(*events, name: nil, &ruby_block)
             # Ensure there is a block.
             ruby_block = proc {} unless block_given?
             # Preprocess the events.
@@ -1257,7 +1263,8 @@ module HDLRuby::High
                 event.respond_to?(:to_event) ? event.to_event : event
             end
             # Create and add the resulting behavior.
-            self.add_behavior(Behavior.new(:par,*events,&ruby_block))
+            self.add_behavior(Behavior.new(:par,*events,name: name,
+                                           &ruby_block))
         end
 
         # Declares a high-level timed behavior built by executing +ruby_block+.
@@ -2271,6 +2278,22 @@ module HDLRuby::High
     end
 
 
+    ## Methods for loading external files.
+
+    # Require a verilog file.
+    def require_verilog(filename)
+      # Converts the file to HDLRuby.
+      if Kernel.system("v2hdr", "#{filename}", "#{filename}.rb") then
+        # Success, require the resulting file.
+        require "#{Dir.pwd}/#{filename}.rb"
+      else
+        # Failure.
+        raise AnyError, 
+          "Could not load Verilog HDL file: #{filename}."
+      end
+    end
+
+
 
     # Classes describing harware instances.
 
@@ -4558,20 +4581,19 @@ module HDLRuby::High
         High = HDLRuby::High
 
         # Creates a new behavior executing +block+ activated on a list of
-        # +events+, and built by executing +ruby_block+.
+        # +events+, possible name (of main block) +name+ and built by
+        # executing +ruby_block+.
         # +mode+ can be either :seq or :par for respectively sequential or
         # parallel.
-        def initialize(mode,*events,&ruby_block)
+        # def initialize(mode, *events, &ruby_block)
+        def initialize(mode, *events, name: nil, &ruby_block)
             # Initialize the behavior with it.
             super(nil)
-            # # Save the Location for debugging information
-            # @location = caller_locations
-            # # Sets the current behavior
-            # @@cur_behavior = self
             # Add the events (they may be hierarchical to flatten)
             events.flatten.each { |event| self.add_event(event) }
             # Create and add the block.
-            self.block = High.make_block(mode,&ruby_block)
+            # self.block = High.make_block(mode,&ruby_block)
+            self.block = High.make_block(mode,*name,&ruby_block)
             # # Unset the current behavior
             # @@cur_behavior = nil
         end
@@ -4866,6 +4888,11 @@ module HDLRuby::High
             to_expr
         end
 
+        # Converts to a new dealy in fentoseconds.
+        def fs
+          return Delay.new(self,:fs)
+        end
+
         # Converts to a new delay in picoseconds.
         def ps
             return Delay.new(self,:ps)

data/lib/HDLRuby/hruby_tools.rb

@@ -7,7 +7,6 @@ module HDLRuby
 # General tools for handling HDLRuby objects
 #######################################################
 
-
     # Method and attribute for generating an absolute uniq name.
     # Such names cannot be used in HDLRuby::High code, but can be used
     # to generate such code.

data/lib/HDLRuby/v2hdr.rb

@@ -0,0 +1,39 @@
+require "HDLRuby/verilog_hruby.rb"
+
+parser = VerilogTools::Parser.new
+
+ast = nil
+
+HELP = "Usage: v2hdr <input verilog file name> <output HDLRuby file name>" 
+
+if  ARGV[0] == "--help" then
+  puts HELP
+  exit
+end
+
+unless ARGV.size == 2 then
+  puts HELP
+  exit(1)
+end
+
+if ARGV[0] == ARGV[1] then
+  puts "Error: input and output files are identical."
+  exit(1)
+end
+
+begin
+  ast = parser.run(filename: ARGV[0], compress: true)
+rescue => error
+  puts error
+  exit(1)
+end
+
+hdlruby = ""
+begin
+  hdlruby = ast.to_HDLRuby
+rescue => error
+  puts error
+  exit(1)
+end
+
+File.open(ARGV[1],"w") { |f| f.write(hdlruby) }