HDLRuby 2.4.27 → 2.4.28

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 68d4b96d98a37f1398d44249498d5bb82e977776d5f3e28a930de98ed8ab5ece
-  data.tar.gz: 6a7c8b57cf47d42f541b04c34765c5b05e08d93a64eaa66e1ca2048b461682a5
+  metadata.gz: ad6c03f726ed838a4d5456f41c4b0f295e4ca7d10ca8585ee8f8c011f7f2fd23
+  data.tar.gz: a59727e177be4d5ff3eb740d210fad37bd4ba9ea6296a8cfed84495a7122411d
 SHA512:
-  metadata.gz: 8c5fd477685906abd21772655ccd1e9c40efdb4069bae0ffbadc9206dc0ea2df2110e983ae08875feec18c1d8e26937e8574aa596c07b946ec9e6ed1ed83714e
-  data.tar.gz: 6a7fd8f88a307d13d100a63fc774ac70452dae9fc444642ceb038dd3b50ad98eb0318b422412dc4efc77ae858d29ff58c0e66b0c5179806cb0b16854b9ff1cef
+  metadata.gz: dc19bcb5b44267c6506a9a1b3547d516b565a2a3ea997bf2ab5cada119caafb0fee09220c7da2e92321562ed2588dc5b6c58c6c697d3230daa8942c00fb731f6
+  data.tar.gz: c6849492302732600fe232d73f6984c4fe1a94e4d818349d5400fb15979eecc6b2b32d71a81b50f09713c5143236e13f330f763ea98beeda4a939d77b8d2fba9

data/lib/HDLRuby/hdr_samples/seqpar_bench.rb

@@ -0,0 +1,59 @@
+# require "../hruby_low2c.rb"
+
+
+
+# A system for testing the execution of par block in seq block.
+system :seqpar_bench do
+
+    inner :rst, :clk
+    signed[8].inner :a, :b, :c, :d
+    signed[8].inner :out
+
+    seq(clk.posedge) do
+        hif(rst) do
+            a <= 0
+            b <= 0
+            c <= 0
+            d <= 0
+        end
+        helse do
+            a <= a + 1
+            b <= a + 2
+            par do
+                c <= b + 3
+                d <= c + 4
+            end
+            a <= d + 5
+        end
+    end
+
+    out <= a
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        rst <= 1
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        rst <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        !20.ns
+    end
+end

data/lib/HDLRuby/hdrcc.rb

@@ -20,6 +20,7 @@ require 'HDLRuby/hruby_low_with_var'
 require 'HDLRuby/hruby_low_without_concat'
 require 'HDLRuby/hruby_low_without_connection'
 require 'HDLRuby/hruby_low_casts_without_expression'
+require 'hruby_low_without_parinseq'
 require 'HDLRuby/hruby_low_cleanup'
 
 require 'HDLRuby/hruby_verilog.rb'
@@ -583,6 +584,7 @@ elsif $options[:verilog] then
         systemT.to_global_systemTs!
         # systemT.break_types!
         # systemT.expand_types!
+        systemT.par_in_seq2seq!
         systemT.initial_concat_to_timed!
         systemT.with_port!
     end

data/lib/HDLRuby/hruby_low_without_parinseq.rb

@@ -0,0 +1,151 @@
+require 'HDLRuby'
+require 'HDLRuby/hruby_tools'
+require 'HDLRuby/hruby_low_mutable'
+
+
+module HDLRuby::Low
+
+
+##
+# Converts par blocks within seq blocks to seq blocks.
+# For matching the executing model of Verilog.
+#
+########################################################################
+    
+
+    ## Extends the SystemT class with functionality for converting par blocks
+    #  within seq blocks to seq blocks.
+    class SystemT
+
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            self.scope.par_in_seq2seq!
+        end
+    end
+
+    ## Extends the Scope class with functionality for breaking assingments
+    #  to concats.
+    class Scope
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            # Recruse on the sub scopes.
+            self.each_scope(&:par_in_seq2seq!)
+            # Recurse on the block.
+            self.each_behavior do |behavior|
+                behavior.block.par_in_seq2seq!
+            end
+        end
+    end
+
+
+    ## Extends the Statement class with functionality for breaking assingments
+    #  to concats.
+    class Statement
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            # By default nothing to do.
+            return self
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            # By default nothing to do.
+            return self
+        end
+    end
+
+
+    ## Extends the If class with functionality for breaking assingments
+    #  to concats.
+    class If
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            self.yes.par_in_seq2seq!
+            self.each_noif do |cond,blk|
+                blk.par_in_seq2seq!
+            end
+            self.no.par_in_seq2seq! if self.no
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            self.to_seq!
+            self.each_noif do |cond,blk|
+                blk.to_seq!
+            end
+            self.no.to_seq! if self.no
+        end
+    end
+
+
+    ## Extends the Case class with functionality for breaking assingments
+    #  to concats.
+    class Case
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            self.each_when do |w|
+                w.statement.par_in_seq2seq!
+            end
+            self.default.par_in_seq2seq! if self.default
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            self.each_when do |w|
+                w.statement.to_seq!
+            end
+            self.default.to_seq! if self.default
+        end
+    end
+
+
+    ## Extends the Block class with functionality for breaking assingments
+    #  to concats.
+    class Block
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            # Recurse on the sub blocks.
+            self.each_statement(&:par_in_seq2seq!)
+            # Is the current block a seq block?
+            if self.mode == :seq then
+                # Yes, convert its inner par blocks to seq blocks.
+                self.each_statement do |statement|
+                    if (statement.is_a?(Block)) then
+                        statement.to_seq! if statement.mode == :par
+                    end
+                end
+            end
+            return self
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            if self.mode == :par then
+                # Need to convert.
+                # First recurse on the sub blocks.
+                self.each_statement(&:to_seq!)
+                # Now replace each left value by a new signal for
+                # differed assingment in seq.
+                differeds = []
+                self.each_statement do |statement|
+                    left = statement.left
+                    if statement.is_a?(Transmit) then
+                        sig = SignalI.new(HDLRuby.uniq_name,left.type)
+                        self.add_inner(sig)
+                        diff = RefName.new(left.type,RefThis.new,sig.name)
+                        differeds << [left,diff]
+                        statement.set_left!(diff)
+                    end
+                end
+                # Adds the differed assignments.
+                differeds.each do |left,diff|
+                    self.add_statement(Transmit.new(left.clone,diff.clone))
+                end
+                # Change the mode.
+                self.set_mode!(:seq)
+            end
+            return self
+        end
+    end
+
+end

data/lib/HDLRuby/hruby_verilog.rb

@@ -14,6 +14,9 @@ module HDLRuby::Low
     # The list of base types used both in verilog and HDLRuby
     VERILOG_BASE_TYPES = ["signed"]
 
+    # The list of signals that are actually verilog regs.
+    VERILOG_REGS = []
+
 
 # Sample of very handy for programming.
 # puts "class=#{self.yes.class}"       # Confirm class of self.yes.
@@ -25,7 +28,7 @@ module HDLRuby::Low
 # end
 
 # Global variable used for indentation and structure (temporary).
-$space_count = 0   # Count used for increasing indent by if statement. (temporary)
+# $space_count = 0   # Count used for increasing indent by if statement. (temporary)
 $vector_reg = ""   # For storing signal type at structure declaration. (temporary)
 $vector_cnt = 0    # For allocating numbers at structure declaration.  (temporary)
 
@@ -101,9 +104,11 @@ end
 # Enhance Transmit with generation of verilog code.
 class Transmit
     # Converts the system to Verilog code.
-    def to_verilog(mode = nil)
+    # def to_verilog(mode = nil)
+    def to_verilog(spc = 3)
         # Determine blocking assignment or nonblocking substitution from mode and return it.
-        code = "#{self.left.to_verilog} #{mode == "seq" ? "=" : "<="} #{self.right.to_verilog};\n"
+        # code = "#{self.left.to_verilog} #{mode == "seq" ? "=" : "<="} #{self.right.to_verilog};\n"
+        code = "#{" " * spc}#{self.left.to_verilog} #{self.block.mode == :seq ? "=" : "<="} #{self.right.to_verilog};"
         return code
     end
 end
@@ -111,12 +116,68 @@ end
 # To scheduling to the Block.
 # Enhance Block with generation of verilog code.
 class Block
-    # Converts the system to Verilog code.
-    def to_verilog(mode = nil)
-        # No translation is done in this class.
-        puts "Block to_verilog not found" # For debugging
+    # # Converts the system to Verilog code.
+    # def to_verilog(mode = nil)
+    #     # No translation is done in this class.
+    #     puts "Block to_verilog not found" # For debugging
+    # end
+
+    # Converts the system to Verilog code adding 'spc' spaces at the begining
+    # of each line.
+    def to_verilog(spc = 3)
+            code = "begin"
+            code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
+            code << "\n" if block.each_inner.any?
+            # Declaration of "inner" part within "always".
+            block.each_inner do |inner|
+                # if regs.include?(inner.name) then
+                if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
+                    # code << "      reg"
+                    code << "#{" " * (spc+3)}reg"
+                else
+                    code << "#{" " * (spc+3)}wire"
+                end
+
+                # Variable has "base", but if there is width etc, it is not in "base".
+                # It is determined by an if.
+                if inner.type.base? 
+                    if inner.type.base.base? 
+                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+                    else
+                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+                    end
+                else
+                    # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                    code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+                end
+                if inner.value then
+                    # There is an initial value.
+                    code << " = #{inner.value.to_verilog}"
+                end
+                code << ";\n"
+            end
+
+            # Translate the block that finished scheduling.
+            block.each_statement do |statement|
+                #code  << "\n      #{statement.to_verilog(behavior.block.mode.to_s)}"
+                # code  << "\n#{" "*spc}#{statement.to_verilog(behavior.block.mode.to_s)}"
+                if statement.is_a?(Block) then
+                    code << "\n#{" " * (spc+3)}#{statement.to_verilog(spc+3)}"
+                else
+                    code  << "\n#{statement.to_verilog(spc+3)}"
+                end
+            end
+            # Close the block."
+            code << "\n#{" "*spc}end"
+            return code
     end
 
+
+
+
+
     # Extract and convert to verilog the TimeRepeat statements.
     # NOTE: work only on the current level of the block (should be called
     # through each_block_deep).
@@ -136,7 +197,7 @@ class Block
             # Declaration of "inner" part within "always".
             block.each_inner do |inner|
                 # if regs.include?(inner.name) then
-                if regs.include?(inner.to_verilog) then
+                if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                     code << "      reg"
                 else
                     code << "      wire"
@@ -1431,66 +1492,82 @@ class Value
     end
 end
 
+
 # Used to transrate if.
 # Enhance If with generation of verilog code.
 class If
-    # Converts the system to Verilog code.
-    def to_verilog(mode = nil)
+    # # Converts the system to Verilog code.
+    # def to_verilog(mode = nil)
+    # Converts to Verilog code, checking adding 'spc' spaces at the begining
+    # of each line.
+    def to_verilog(spc = 3)
 
         $blocking = false
 
-        if ($space_count == 0) then
-            result = "   " * ($space_count)  # Indented based on space_count.
-        else
-            result = ""
-        end
-        $space_count += 1                  # Add count to be used for indentation.
+        # if ($space_count == 0) then
+        #     result = "   " * ($space_count)  # Indented based on space_count.
+        # else
+        #     result = ""
+        # end
+        # $space_count += 1                  # Add count to be used for indentation.
+        result = " " * spc  # Indented based on space_count.
 
-        result << "if (#{self.condition.to_verilog}) begin\n"
+        # result << "if (#{self.condition.to_verilog}) begin\n"
+        result << "if (#{self.condition.to_verilog}) "
 
 
         # Check if there is yes (if) and output yes or less.
         if self.respond_to? (:yes)
-            self.yes.each_statement do |statement|
-                result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
-            end
-            result << "#{"   " * $space_count}   end\n"
+            # self.yes.each_statement do |statement|
+            #     result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
+            # end
+            # result << "#{"   " * $space_count}   end\n"
+            result << self.yes.to_verilog(spc)
         end
 
         # If noif (else if) exists, it outputs it.
         # Since noif is directly under, respond_to is unnecessary.
         self.each_noif do |condition, block|
-            result << "#{"   " * $space_count}   else if (#{condition.to_verilog}) begin\n"
-            block.each_statement do |statement|
-                result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
-            end
-            result << "#{"   "* $space_count}   end\n"
+            # result << "#{"   " * $space_count}   else if (#{condition.to_verilog}) begin\n"
+            result << "\n#{" "*spc}else if (#{condition.to_verilog}) "
+            # block.each_statement do |statement|
+            #     result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
+            # end
+            # result << "#{"   "* $space_count}   end\n"
+            result << block.to_verilog(spc)
         end
 
         # Check if there is no (else) and output no or less.
-        if self.no.respond_to? (:mode)
-            result << "#{"   " * $space_count}   else begin\n"
-            self.no.each_statement do |statement|
-                result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
-            end
-            result << "#{"   " * $space_count}   end\n"
+        if self.no.respond_to?(:mode)
+            # result << "#{"   " * $space_count}   else begin\n"
+            result << "\n#{" " * spc}else "
+            # self.no.each_statement do |statement|
+            #     result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
+            # end
+            # result << "#{"   " * $space_count}   end\n"
+            result << self.no.to_verilog(spc)
         end
 
-        $space_count -= 1 # Since the output ends, reduce the count.
+        # $space_count -= 1 # Since the output ends, reduce the count.
         return result
     end
 end
 
 # Used to translate case
 class Case
-    def to_verilog(mode = nil)
+    # def to_verilog(mode = nil)
+    #
+    # Converts to Verilog code, checking if variables are register
+    # or wire adding 'spc' spaces at the begining of each line.
+    def to_verilog(spc = 3)
 
-        if ($space_count == 0) then
-            result = "   " * ($space_count) # Indented based on space_count.
-        else
-            result = ""
-        end
-        $space_count += 1                 # Add count to be used for indentation.
+        # if ($space_count == 0) then
+        #     result = "   " * ($space_count) # Indented based on space_count.
+        # else
+        #     result = ""
+        # end
+        # $space_count += 1                 # Add count to be used for indentation.
+        result = " " * spc # Indented based on space_count.
 
         result = ""
         result << "case(#{self.value.to_verilog})\n"
@@ -1498,40 +1575,55 @@ class Case
         # n the case statement, each branch is partitioned by when. Process each time when.
         self.each_when do |whens| 
             # Reads and stores the numbers and expressions stored in when.
-            result << "      " + "   " *$space_count + "#{whens.match.to_verilog}: "
-            if whens.statement.each_statement.count > 1 then
-                result << "begin\n"
-                whens.statement.each_statement do |statement|
-                    result << "                  "+ "   " *$space_count +"#{statement.to_verilog}"
-                end
-                result << "             " + "   " *$space_count + "end\n"
-            elsif whens.statement.each_statement.count == 1 then
-                whens.statement.each_statement do |statement|
-                    result << "#{statement.to_verilog}"
-                end
+            # result << "      " + "   " *$space_count + "#{whens.match.to_verilog}: "
+            result << " " * (spc+3) + "#{whens.match.to_verilog}: "
+            
+            # if whens.statement.each_statement.count > 1 then
+            #     result << "begin\n"
+            #     whens.statement.each_statement do |statement|
+            #         result << "                  "+ "   " *$space_count +"#{statement.to_verilog}"
+            #     end
+            #     result << "             " + "   " *$space_count + "end\n"
+            # elsif whens.statement.each_statement.count == 1 then
+            #     whens.statement.each_statement do |statement|
+            #         result << "#{statement.to_verilog}"
+            #     end
+            # else
+            #     # Empty statement case.
+            #     result << "\n"
+            # end
+            if whens.statement.each_statement.count >= 1 then
+                result << whens.statement.to_verilog(spc+3)
             else
-                # Empty statement case.
                 result << "\n"
             end
         end
-        # The default part is stored in default instead of when. Reads and processes in the same way as when.
+        # # The default part is stored in default instead of when. Reads and processes in the same way as when.
+        # if self.default then
+        #     if self.default.each_statement.count > 1 then
+        #         result << "      " + "   " *$space_count + "default: begin\n"
+        #         self.default.each_statement do |statement|
+        #             result << "                  " + "   " *$space_count + "#{statement.to_verilog}"
+        #         end
+        #         result << "                  end\n"
+        #     elsif self.default.each_statement.count == 1 then
+        #         result << "      " + "   " *$space_count + "default: "
+        #         self.default.each_statement do |statement|
+        #             result << "#{statement.to_verilog}"
+        #         end
+        #     end  
+        # end
         if self.default then
-            if self.default.each_statement.count > 1 then
-                result << "      " + "   " *$space_count + "default: begin\n"
-                self.default.each_statement do |statement|
-                    result << "                  " + "   " *$space_count + "#{statement.to_verilog}"
-                end
-                result << "                  end\n"
-            elsif self.default.each_statement.count == 1 then
-                result << "      " + "   " *$space_count + "default: "
-                self.default.each_statement do |statement|
-                    result << "#{statement.to_verilog}"
-                end
-            end  
+            if self.default.each_statement.count >= 1 then
+                result << self.default.each_statement.to_verilog(spc+3)
+            else
+                result << "\n"
+            end
         end
-        result << "   " + "   " *$space_count + "endcase\n" # Conclusion.
+        # result << "   " + "   " *$space_count + "endcase\n" # Conclusion.
+        result << " " * spc + "endcase\n" # Conclusion.
 
-        $space_count -= 1           # Since the output ends, reduce the count.
+        # $space_count -= 1           # Since the output ends, reduce the count.
         return result               # Return case after translation.
     end
 end
@@ -1697,8 +1789,9 @@ end
 # Look at the unit of time, convert the time to ps and output it.
 # One of two people, TimeWait and Delay.
 class TimeWait
-    def to_verilog(mode=nil)
-        return self.delay.to_verilog + "\n"
+    # def to_verilog(mode=nil)
+    def to_verilog(spc = 3)
+        return (" " * spc) + self.delay.to_verilog + "\n"
     end
 end
 class Delay
@@ -1776,15 +1869,9 @@ class SystemT
 
     # Converts the system to Verilog code.
     def to_verilog
-        # Preprocessing
-        # Force seq block to par: ULTRA TEMPORARY! ICIICI
-        self.each_behavior do |behavior|
-            behavior.each_block_deep do |block|
-                block.set_mode!(:par) unless block.is_a?(TimeBlock)
-            end
-        end
         # Detect the registers
-        regs = []
+        # regs = []
+        HDLRuby::Low::VERILOG_REGS.clear
         # The left values.
         self.each_behavior do |behavior|
             # behavior.block.each_statement do |statement|
@@ -1792,7 +1879,9 @@ class SystemT
             # end
             behavior.each_block_deep do |block|
                 block.each_statement do |statement|
-                    regs << statement.left.to_verilog if statement.is_a?(Transmit)
+                    if statement.is_a?(Transmit)
+                        HDLRuby::Low::VERILOG_REGS << statement.left.to_verilog
+                    end
                 end
             end
         end
@@ -1809,19 +1898,27 @@ class SystemT
         # # puts "Now regs has clk?: #{regs.include?("clk")}"
         # And the initialized signals.
         self.each_output do |output|
-            regs << output.to_verilog if output.value
+            # regs << output.to_verilog if output.value
+            HDLRuby::Low::VERILOG_REGS << output.to_verilog if output.value
         end
         self.each_inner do |inner|
-            regs << inner.to_verilog if inner.value
+            # regs << inner.to_verilog if inner.value
+            HDLRuby::Low::VERILOG_REGS << inner.to_verilog if inner.value
         end
         # And the array types signals.
         self.each_signal do |sig|
-            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
-            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
+            # # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
+            if sig.type.vector? && sig.type.base.vector? then
+                HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            end
         end
         self.each_inner do |sig|
-            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
-            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
+            # # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
+            if sig.type.vector? && sig.type.base.vector? then
+                HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            end
         end
 
         # Code generation
@@ -1890,7 +1987,8 @@ class SystemT
                 $vector_reg = "#{output.to_verilog}"
                 $vector_cnt = 0
                 output.type.each_type do |type|
-                    if regs.include?(type.name) then
+                    # if regs.include?(type.name) then
+                    if HDLRuby::Low::VERILOG_REGS.include?(type.name) then
                         code << "   output reg"
                     else
                         code << "   output"
@@ -1906,7 +2004,8 @@ class SystemT
                 end        
             else
                 # if regs.include?(output.name) then
-                if regs.include?(output.to_verilog) then
+                # if regs.include?(output.to_verilog) then
+                if HDLRuby::Low::VERILOG_REGS.include?(output.to_verilog) then
                     code << "   output reg"
                 else
                     code << "   output"
@@ -1937,8 +2036,9 @@ class SystemT
 
         # Declare "inner".
         self.each_inner do |inner|
-            # if regs.include?(inner.name) then
-            if regs.include?(inner.to_verilog) then
+            # # if regs.include?(inner.name) then
+            # if regs.include?(inner.to_verilog) then
+            if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                 code << "   reg"
             else
                 code << "   wire"
@@ -1966,8 +2066,9 @@ class SystemT
         # If there is scope in scope, translate it.
         self.each_scope do |scope|
             scope.each_inner do |inner|
-                # if regs.include?(inner.name) then
-                if regs.include?(inner.to_verilog) then
+                # # if regs.include?(inner.name) then
+                # if regs.include?(inner.to_verilog) then
+                if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                     code << "   reg "
                 else
                     code << "   wire "
@@ -2058,7 +2159,8 @@ class SystemT
                     code << blk.repeat_to_verilog!
                 end
                 # And generate an initial block.
-                code << "   initial begin\n"
+                # code << "   initial begin\n"
+                code << "   initial "
             else
                 # Generate a standard process.
                 code << "   always @( "
@@ -2083,54 +2185,57 @@ class SystemT
                         code << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
                     end
                 end
-                code << " ) begin\n"
+                # code << " ) begin\n"
+                code << " ) "
             end
 
-            # Perform "scheduling" using the method "flatten".
-            block = behavior.block.flatten(behavior.block.mode.to_s)
-
-            # Declaration of "inner" part within "always".
-            block.each_inner do |inner|
-                # if regs.include?(inner.name) then
-                if regs.include?(inner.to_verilog) then
-                    code << "      reg"
-                else
-                    code << "      wire"
-                end
-
-                # Variable has "base", but if there is width etc, it is not in "base".
-                # It is determined by an if.
-                if inner.type.base? 
-                    if inner.type.base.base? 
-                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
-                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
-                    else
-                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
-                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
-                    end
-                else
-                    # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
-                    code << " #{inner.type.to_verilog}#{inner.to_verilog}"
-                end
-                if inner.value then
-                    # There is an initial value.
-                    code << " = #{inner.value.to_verilog}"
-                end
-                code << ";\n"
-            end
+            # # Perform "scheduling" using the method "flatten".
+            # block = behavior.block.flatten(behavior.block.mode.to_s)
+            # code << block.to_verilog(regs)
+            code << behavior.block.to_verilog
+
+            # # Declaration of "inner" part within "always".
+            # block.each_inner do |inner|
+            #     # if regs.include?(inner.name) then
+            #     if regs.include?(inner.to_verilog) then
+            #         code << "      reg"
+            #     else
+            #         code << "      wire"
+            #     end
+
+            #     # Variable has "base", but if there is width etc, it is not in "base".
+            #     # It is determined by an if.
+            #     if inner.type.base? 
+            #         if inner.type.base.base? 
+            #             # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+            #             code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+            #         else
+            #             # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+            #             code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+            #         end
+            #     else
+            #         # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+            #         code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+            #     end
+            #     if inner.value then
+            #         # There is an initial value.
+            #         code << " = #{inner.value.to_verilog}"
+            #     end
+            #     code << ";\n"
+            # end
 
-            # Translate the block that finished scheduling.
-            block.each_statement do |statement|
-                code  << "\n      #{statement.to_verilog(behavior.block.mode.to_s)}"
-            end
+            # # Translate the block that finished scheduling.
+            # block.each_statement do |statement|
+            #     code  << "\n      #{statement.to_verilog(behavior.block.mode.to_s)}"
+            # end
 
-            $fm.fm_par.clear()
+            # $fm.fm_par.clear()
 
-            code << "\n   end\n\n"
+            # code << "\n   end\n\n"
         end
 
         # Conclusion.
-        code << "endmodule"
+        code << "\nendmodule"
         return code
     end
 end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.27"
+  VERSION = "2.4.28"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.27
+  version: 2.4.28
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-01-05 00:00:00.000000000 Z
+date: 2021-01-10 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -116,6 +116,7 @@ files:
 - lib/HDLRuby/hdr_samples/register_with_code_bench.rb
 - lib/HDLRuby/hdr_samples/rom.rb
 - lib/HDLRuby/hdr_samples/ruby_fir_hw.rb
+- lib/HDLRuby/hdr_samples/seqpar_bench.rb
 - lib/HDLRuby/hdr_samples/struct.rb
 - lib/HDLRuby/hdr_samples/sumprod.rb
 - lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb
@@ -221,6 +222,7 @@ files:
 - lib/HDLRuby/hruby_low_without_connection.rb
 - lib/HDLRuby/hruby_low_without_namespace.rb
 - lib/HDLRuby/hruby_low_without_outread.rb
+- lib/HDLRuby/hruby_low_without_parinseq.rb
 - lib/HDLRuby/hruby_low_without_select.rb
 - lib/HDLRuby/hruby_serializer.rb
 - lib/HDLRuby/hruby_tools.rb