HDLRuby 2.4.19 → 2.4.20
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/with_connector.rb +10 -1
- data/lib/HDLRuby/std/connector.rb +22 -3
- data/lib/HDLRuby/std/memory.rb +121 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: fd6292fe897c939784b2d10ae3e69e69eec7149be02fbc077b9ae789af840825
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4
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data.tar.gz: cd3ead86ae5b63976cab3d45db537f60a984ca65b0355dadaa755d1b6cbe0b89
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SHA512:
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-
metadata.gz:
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-
data.tar.gz:
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metadata.gz: 7d33e055f706df8d06d6bd7578002a399c695f5a6705fce523a033a8d9954a74b44e1a337ac851a49a68a0c8d5a3fe42326a26b5d92003bb7d17dc90f5ed27a8
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7
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data.tar.gz: 8f49e18b9dbfd2ce0a5676e558c6054258809876f610ec3e35eda8ad4bf18ba9834aa11c6229ceb5e75b42649a353603da854a57b9f72432dc0b6459b1e35d61
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@@ -130,6 +130,7 @@ system :with_connectors do
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130
130
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[4].inner :counter
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131
131
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[4*4].inner :res
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132
132
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inner :ack_in, :ack_out
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133
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+
inner :dup_req, :dup_ack
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133
134
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134
135
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# The input queue.
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135
136
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queue(bit[4],4,clk,rst).(:in_qu)
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@@ -143,7 +144,7 @@ system :with_connectors do
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143
144
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queue(bit[4*4],4,clk,rst).(:out_qu)
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144
145
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145
146
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# Connect the input queue to the middle queues.
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146
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-
duplicator(bit[4],clk.negedge,in_qu,mid_qus)
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147
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+
duplicator(bit[4],clk.negedge,in_qu,mid_qus,dup_req,dup_ack)
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147
148
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148
149
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# Connect the middle queues to the output queue.
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149
150
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merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
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@@ -221,6 +222,7 @@ system :with_connectors do
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221
222
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timed do
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222
223
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clk <= 0
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223
224
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rst <= 0
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225
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+
dup_req <= 0
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224
226
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!10.ns
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225
227
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clk <= 1
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226
228
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!10.ns
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@@ -235,6 +237,13 @@ system :with_connectors do
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235
237
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!10.ns
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236
238
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clk <= 0
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237
239
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rst <= 0
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240
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+
4.times do
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241
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!10.ns
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242
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clk <= 1
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243
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+
!10.ns
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244
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clk <= 0
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245
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end
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246
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dup_req <= 1
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238
247
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16.times do
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239
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!10.ns
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240
249
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clk <= 1
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@@ -9,13 +9,28 @@ module HDLRuby::High::Std
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9
9
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# channel +in_ch+ and connect it to channels +out_chs+ with data of
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10
10
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# +typ+.
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11
11
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# The duplication is done according to event +ev+.
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12
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-
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12
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# The optional req and ack arguments are the signals for controlling the
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13
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# duplicator using a handshake protocol. If set to nil, the duplicator
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14
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# runs automatically.
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15
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function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
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13
16
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ev = ev.poswedge unless ev.is_a?(Event)
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14
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-
inner :in_ack
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17
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+
inner :in_ack
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18
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+
inner :in_req
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15
19
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out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
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16
20
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typ.inner :data
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17
21
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par(ev) do
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18
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-
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22
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if (ack) then
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23
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# Output ack mode.
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24
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ack <= 0
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25
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end
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26
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if (req) then
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27
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# Input request mode.
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28
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in_req <= 0
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29
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hif(req) { in_req <= 1 }
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30
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else
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31
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# Automatic mode.
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32
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in_req <= 1
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33
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end
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19
34
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out_acks.each { |ack| ack <= 0 }
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20
35
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out_acks.each do |ack|
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21
36
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hif(ack == 1) { in_req <= 0 }
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@@ -30,6 +45,10 @@ module HDLRuby::High::Std
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30
45
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end
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31
46
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hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
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32
47
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out_acks.each { |ack| ack <= 0 }
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48
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if (ack) then
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49
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# Output ack mode.
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50
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ack <= 1
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51
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end
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33
52
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end
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34
53
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end
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35
54
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end
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data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -1704,6 +1704,127 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
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1704
1704
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1705
1705
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end
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1706
1706
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1707
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+
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1708
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# Queue memory of +size+ elements of +typ+ typ, syncrhonized on +clk+
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1709
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# (positive and negative edges) and reset on +rst+.
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1710
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# At each rising edge of +clk+ a read and a write is guaranteed to be
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1711
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# completed provided they are triggered.
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1712
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#
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1713
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# NOTE: this channel does not have any branch.
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1714
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HDLRuby::High::Std.channel(:mem_queue) do |typ,size,clk,rst|
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1715
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# The inner buffer of the queue.
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1716
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typ[-size].inner :buffer
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1717
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# The read and write pointers.
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1718
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[size.width].inner :rptr, :wptr
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1719
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# The read and write command signals.
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1720
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inner :rreq, :wreq
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1721
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# The read and write ack signals.
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1722
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inner :rack, :wack
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1723
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# The read/write data registers.
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1724
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typ.inner :rdata, :wdata
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1725
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+
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1726
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# The flags telling of the channel is synchronized
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1727
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inner :rsync, :wsync
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1728
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+
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1729
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# The process handling the decoupled access to the buffer.
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1730
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par(clk.posedge) do
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1731
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hif(rst) { rptr <= 0; wptr <= 0 }
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1732
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helse do
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1733
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hif(~rsync) do
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1734
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hif (~rreq) { rack <= 0 }
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1735
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hif(rreq & (~rack) & (rptr != wptr)) do
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1736
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rdata <= buffer[rptr]
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1737
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rptr <= (rptr + 1) % depth
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1738
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rack <= 1
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1739
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end
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1740
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end
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1741
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+
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1742
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hif(~wsync) do
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1743
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hif (~wreq) { wack <= 0 }
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1744
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hif(wreq & (~wack) & (((wptr+1) % size) != rptr)) do
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1745
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buffer[wptr] <= wdata
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1746
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wptr <= (wptr + 1) % size
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1747
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wack <= 1
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1748
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+
end
|
1749
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+
end
|
1750
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+
end
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1751
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+
end
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1752
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+
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1753
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reader_output :rreq, :rptr, :rsync
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1754
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reader_input :rdata, :rack, :wptr, :buffer
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1755
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+
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1756
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# The read primitive.
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1757
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reader do |blk,target|
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1758
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+
if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
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1759
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# Same clk event, synchrone case: perform a direct access.
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1760
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# Now perform the access.
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1761
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top_block.unshift do
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1762
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rsync <= 1
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1763
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rreq <= 0
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1764
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+
end
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1765
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+
seq do
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1766
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hif(rptr != wptr) do
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1767
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# target <= rdata
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1768
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target <= buffer[rptr]
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1769
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+
rptr <= (rptr + 1) % size
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1770
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+
blk.call if blk
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1771
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+
end
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1772
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+
end
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1773
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+
else
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1774
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+
# Different clk event, perform a decoupled access.
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1775
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+
top_block.unshift do
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1776
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+
rsync <= 0
|
1777
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+
rreq <= 0
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1778
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+
end
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1779
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+
par do
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1780
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+
hif (~rack) { rreq <= 1 }
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1781
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+
helsif(rreq) do
|
1782
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+
rreq <= 0
|
1783
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+
target <= rdata
|
1784
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+
blk.call if blk
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1785
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+
end
|
1786
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+
end
|
1787
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+
end
|
1788
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+
end
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1789
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+
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1790
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writer_output :wreq, :wdata, :wptr, :wsync, :buffer
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1791
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+
writer_input :wack, :rptr
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1792
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+
|
1793
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+
# The write primitive.
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1794
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+
writer do |blk,target|
|
1795
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+
if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
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1796
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+
# Same clk event, synchrone case: perform a direct access.
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1797
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+
top_block.unshift do
|
1798
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+
wsync <= 1
|
1799
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+
wreq <= 0
|
1800
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+
end
|
1801
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+
hif(((wptr+1) % size) != rptr) do
|
1802
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buffer[wptr] <= target
|
1803
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+
wptr <= (wptr + 1) % size
|
1804
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+
blk.call if blk
|
1805
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+
end
|
1806
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+
else
|
1807
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+
# Different clk event, asynchrone case: perform a decoupled access.
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1808
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+
top_block.unshift do
|
1809
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+
wsync <= 0
|
1810
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+
wreq <= 0
|
1811
|
+
end
|
1812
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+
seq do
|
1813
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+
hif (~wack) do
|
1814
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+
wreq <= 1
|
1815
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+
wdata <= target
|
1816
|
+
end
|
1817
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+
helsif(wreq) do
|
1818
|
+
wreq <= 0
|
1819
|
+
blk.call if blk
|
1820
|
+
end
|
1821
|
+
end
|
1822
|
+
end
|
1823
|
+
end
|
1824
|
+
end
|
1825
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+
|
1826
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+
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1827
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+
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1707
1828
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# HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
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1708
1829
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# # Ensure typ is a type.
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1709
1830
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# typ = typ.to_type
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: HDLRuby
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3
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version: !ruby/object:Gem::Version
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-
version: 2.4.
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version: 2.4.20
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platform: ruby
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authors:
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- Lovic Gauthier
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autorequire:
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bindir: exe
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cert_chain: []
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-
date: 2020-12-
|
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+
date: 2020-12-09 00:00:00.000000000 Z
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dependencies:
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13
13
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- !ruby/object:Gem::Dependency
|
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name: bundler
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