HDLRuby 2.4.9 → 2.4.10

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Files changed (5) hide show
  1. checksums.yaml +4 -4
  2. data/lib/HDLRuby/hdr_samples/with_memory_rom.rb +53 -0
  3. data/lib/HDLRuby/std/memory.rb +92 -13
  4. data/lib/HDLRuby/version.rb +1 -1
  5. metadata +3 -2
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data/lib/HDLRuby/hdr_samples/with_memory_rom.rb ADDED
@@ -0,0 +1,53 @@
1
+ require 'std/memory.rb'
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+
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+ include HDLRuby::High::Std
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+
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+
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+
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+
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+
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+ # A system testing the rom channel.
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+ system :rorm_test do
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+ inner :clk,:rst
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+ [8].inner :value
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+ inner :addr
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+
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+ # Declares a 8-bit-data and 1 element rom address synchronous memory
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+ # on negative edge of clk.
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+ # mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
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+ mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
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+ rd = romI.branch(:rinc)
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+
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+ par(clk.posedge) do
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+ hif(rst) { addr <= 0 }
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+ helse do
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+ rd.read(value)
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+ end
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+ end
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+
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+ timed do
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+ clk <= 0
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+ rst <= 0
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+ !10.ns
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+ clk <= 1
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+ !10.ns
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+ clk <= 0
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+ rst <= 1
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+ !10.ns
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+ clk <= 1
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+ !10.ns
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+ clk <= 0
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+ !10.ns
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+ clk <= 1
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+ !10.ns
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+ clk <= 0
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+ rst <= 0
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+ !10.ns
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+ 10.times do
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+ clk <= 1
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+ !10.ns
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+ clk <= 0
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+ !10.ns
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+ end
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+ end
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+ end
data/lib/HDLRuby/std/memory.rb CHANGED
@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
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  size = size.to_i
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  # Compute the address bus width from the size.
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  awidth = (size-1).width
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+ awidth = 1 if awidth == 0
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  # Ensure clk_e is an event, if not set it to a positive edge.
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  clk_e = clk_e.posedge unless clk_e.is_a?(Event)
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@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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  size = size.to_i
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  # Compute the address bus width from the size.
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  awidth = (size-1).width
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+ awidth = 1 if awidth == 0
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  # Process the table of reset mapping for the branches.
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  # Ensures br_srts is a hash.
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  br_rsts = br_rsts.to_hash
@@ -321,7 +323,12 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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  end
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  helse do
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  # Prepare the read.
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- abus_r <= abus_r + 1
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+ # abus_r <= abus_r + 1
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+ if 2**size.width != size then
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+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
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+ else
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+ abus_r <= abus_r + 1
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+ end
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  trig_r <= 1
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  end
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  end
@@ -382,7 +389,12 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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  end
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  helse do
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  # Prepare the read.
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- abus_r <= abus_r - 1
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+ # abus_r <= abus_r - 1
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+ if 2**size.width != size then
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+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
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+ else
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+ abus_r <= abus_r - 1
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+ end
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  trig_r <= 1
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  end
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  end
@@ -434,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
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  size = size.to_i
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  # Compute the address bus width from the size.
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  awidth = (size-1).width
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+ awidth = 1 if awidth == 0
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  # Process the table of reset mapping for the branches.
438
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  # puts "first br_rsts=#{br_rsts}"
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  # if br_rsts.is_a?(Array) then
@@ -593,7 +606,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
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  end
594
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  helse do
595
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  # Prepare the read.
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- abus_r <= abus_r + 1
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+ # abus_r <= abus_r + 1
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+ if 2**size.width != size then
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+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
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+ else
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+ abus_r <= abus_r + 1
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+ end
597
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  trig_r <= 1
598
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  end
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  end
@@ -630,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
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  # No reset, so can perform the write.
631
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  blk.call if blk
632
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  # Prepare the write.
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- abus_w <= abus_w + 1
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+ # abus_w <= abus_w + 1
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+ if 2**size.width != size then
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+ abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
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+ else
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+ abus_w <= abus_w + 1
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+ end
634
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  trig_w <= 1
635
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  dbus_w <= target
636
659
  end
@@ -692,7 +715,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
692
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  end
693
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  helse do
694
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  # Prepare the read.
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- abus_r <= abus_r - 1
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+ # abus_r <= abus_r - 1
719
+ if 2**size.width != size then
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+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
721
+ else
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+ abus_r <= abus_r - 1
723
+ end
696
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  trig_r <= 1
697
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  end
698
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  end
@@ -729,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
729
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  # No reset, so can perform the write.
730
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  blk.call if blk
731
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  # Prepare the write.
732
- abus_w <= abus_w - 1
760
+ # abus_w <= abus_w - 1
761
+ if 2**size.width != size then
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+ abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
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+ else
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+ abus_w <= abus_w - 1
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+ end
733
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  trig_w <= 1
734
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  dbus_w <= target
735
768
  end
@@ -923,6 +956,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
923
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  reader_input rst_name
924
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  end
925
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  # Declares the address counter.
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+ awidth = size.width-1
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+ awidth = 1 if awidth == 0
926
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  [size.width-1].inner :abus_r
927
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  reader_inout :abus_r
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@@ -946,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
946
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  end
947
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  blk.call if blk
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  # Prepare the next read.
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- abus_r <= abus_r + 1
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+ # abus_r <= abus_r + 1
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+ if 2**size.width != size then
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+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
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+ else
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+ abus_r <= abus_r + 1
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+ end
950
990
  end
951
991
  end
952
992
  end
@@ -985,7 +1025,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
985
1025
  end
986
1026
  blk.call if blk
987
1027
  # Prepare the next write.
988
- abus_w <= abus_w + 1
1028
+ # abus_w <= abus_w + 1
1029
+ if 2**size.width != size then
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+ abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
1031
+ else
1032
+ abus_w <= abus_w + 1
1033
+ end
989
1034
  end
990
1035
  end
991
1036
  end
@@ -1003,6 +1048,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1003
1048
  reader_input rst_name
1004
1049
  end
1005
1050
  # Declares the address counter.
1051
+ awidth = size.width - 1
1052
+ awidth = 1 if awidth == 0
1006
1053
  [size.width-1].inner :abus_r
1007
1054
  reader_inout :abus_r
1008
1055
 
@@ -1026,7 +1073,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1026
1073
  end
1027
1074
  blk.call if blk
1028
1075
  # Prepare the next read.
1029
- abus_r <= abus_r - 1
1076
+ # abus_r <= abus_r - 1
1077
+ if 2**size.width != size then
1078
+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
1079
+ else
1080
+ abus_r <= abus_r - 1
1081
+ end
1030
1082
  end
1031
1083
  end
1032
1084
  end
@@ -1065,7 +1117,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1065
1117
  end
1066
1118
  blk.call if blk
1067
1119
  # Prepare the next write.
1068
- abus_w <= abus_w - 1
1120
+ # abus_w <= abus_w - 1
1121
+ if 2**size.width != size then
1122
+ abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
1123
+ else
1124
+ abus_w <= abus_w - 1
1125
+ end
1069
1126
  end
1070
1127
  end
1071
1128
  end
@@ -1113,7 +1170,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1113
1170
  size = size.to_i
1114
1171
  # Compute the address bus width from the size.
1115
1172
  awidth = (size*nbanks-1).width
1173
+ awidth = 1 if awidth == 0
1116
1174
  awidth_b = (size-1).width # Bank width
1175
+ awidth_b = 1 if awidth_b == 0
1117
1176
  # Ensures br_srts is a hash.
1118
1177
  br_rsts = br_rsts.to_hash
1119
1178
 
@@ -1274,7 +1333,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1274
1333
  blk.call if blk
1275
1334
  end
1276
1335
  # Prepare the read.
1277
- abus_r <= abus_r + 1
1336
+ # abus_r <= abus_r + 1
1337
+ if 2**size.width != size then
1338
+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
1339
+ else
1340
+ abus_r <= abus_r + 1
1341
+ end
1278
1342
  trig_r <= 1
1279
1343
  end
1280
1344
  end
@@ -1310,7 +1374,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1310
1374
  # No reset, so can perform the write.
1311
1375
  blk.call if blk
1312
1376
  # Prepare the write.
1313
- abus_w <= abus_w + 1
1377
+ # abus_w <= abus_w + 1
1378
+ if 2**size.width != size then
1379
+ abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
1380
+ else
1381
+ abus_w <= abus_w + 1
1382
+ end
1314
1383
  trig_w <= 1
1315
1384
  dbus_w <= target
1316
1385
  end
@@ -1351,7 +1420,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1351
1420
  blk.call if blk
1352
1421
  end
1353
1422
  # Prepare the read.
1354
- abus_r <= abus_r - 1
1423
+ # abus_r <= abus_r - 1
1424
+ if 2**size.width != size then
1425
+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
1426
+ else
1427
+ abus_r <= abus_r - 1
1428
+ end
1355
1429
  trig_r <= 1
1356
1430
  end
1357
1431
  end
@@ -1388,6 +1462,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1388
1462
  blk.call if blk
1389
1463
  # Prepare the write.
1390
1464
  abus_w <= abus_w - 1
1465
+ if 2**size.width != size then
1466
+ abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
1467
+ else
1468
+ abus_w <= abus_w - 1
1469
+ end
1391
1470
  trig_w <= 1
1392
1471
  dbus_w <= target
1393
1472
  end
data/lib/HDLRuby/version.rb CHANGED
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.4.9"
2
+ VERSION = "2.4.10"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.4.9
4
+ version: 2.4.10
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-10-15 00:00:00.000000000 Z
11
+ date: 2020-10-16 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -125,6 +125,7 @@ files:
125
125
  - lib/HDLRuby/hdr_samples/with_linear.rb
126
126
  - lib/HDLRuby/hdr_samples/with_loop.rb
127
127
  - lib/HDLRuby/hdr_samples/with_memory.rb
128
+ - lib/HDLRuby/hdr_samples/with_memory_rom.rb
128
129
  - lib/HDLRuby/hdr_samples/with_multi_channels.rb
129
130
  - lib/HDLRuby/hdr_samples/with_reconf.rb
130
131
  - lib/HDLRuby/hdrcc.rb