HDLRuby 2.4.9 → 2.4.10
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/with_memory_rom.rb +53 -0
- data/lib/HDLRuby/std/memory.rb +92 -13
- data/lib/HDLRuby/version.rb +1 -1
- metadata +3 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: d90d9d7ef8c4535bbce1db315a06ec6e85c8efe37ddb07828605f72049f5daf2
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data.tar.gz: d3f6d2fb5cccb840c8385ab8af724f6dcfef2efed5d9d263ef50be104f2aba3a
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 548de87c875473eaf522c8db89d7842cd79f2638be583e85a0b9e143bb21ac89a40e447fb2d8d09f55d67543954d59e7880eceb4e515b96de6f959d3cf48edd6
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7
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data.tar.gz: d8fe03171ac0bada3bc7b30625cd8c874d1d98b72757ad180fc4ec52f9803f243058f423fa9047924d33d2e4350f7f3e9acee0dda3d654175e026ed94edee32e
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@@ -0,0 +1,53 @@
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1
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require 'std/memory.rb'
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2
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3
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include HDLRuby::High::Std
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4
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5
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6
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7
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8
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9
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# A system testing the rom channel.
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10
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system :rorm_test do
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11
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inner :clk,:rst
|
12
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[8].inner :value
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13
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inner :addr
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14
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+
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15
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# Declares a 8-bit-data and 1 element rom address synchronous memory
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16
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# on negative edge of clk.
|
17
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+
# mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
|
18
|
+
mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
|
19
|
+
rd = romI.branch(:rinc)
|
20
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+
|
21
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+
par(clk.posedge) do
|
22
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+
hif(rst) { addr <= 0 }
|
23
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+
helse do
|
24
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+
rd.read(value)
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25
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end
|
26
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+
end
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27
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+
|
28
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timed do
|
29
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+
clk <= 0
|
30
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+
rst <= 0
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31
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+
!10.ns
|
32
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+
clk <= 1
|
33
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+
!10.ns
|
34
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+
clk <= 0
|
35
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+
rst <= 1
|
36
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+
!10.ns
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37
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+
clk <= 1
|
38
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+
!10.ns
|
39
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+
clk <= 0
|
40
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+
!10.ns
|
41
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+
clk <= 1
|
42
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!10.ns
|
43
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+
clk <= 0
|
44
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+
rst <= 0
|
45
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+
!10.ns
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46
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+
10.times do
|
47
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+
clk <= 1
|
48
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+
!10.ns
|
49
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+
clk <= 0
|
50
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+
!10.ns
|
51
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+
end
|
52
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end
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53
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end
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data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
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|
34
34
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size = size.to_i
|
35
35
|
# Compute the address bus width from the size.
|
36
36
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awidth = (size-1).width
|
37
|
+
awidth = 1 if awidth == 0
|
37
38
|
# Ensure clk_e is an event, if not set it to a positive edge.
|
38
39
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clk_e = clk_e.posedge unless clk_e.is_a?(Event)
|
39
40
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@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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|
209
210
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size = size.to_i
|
210
211
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# Compute the address bus width from the size.
|
211
212
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awidth = (size-1).width
|
213
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+
awidth = 1 if awidth == 0
|
212
214
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# Process the table of reset mapping for the branches.
|
213
215
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# Ensures br_srts is a hash.
|
214
216
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br_rsts = br_rsts.to_hash
|
@@ -321,7 +323,12 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
321
323
|
end
|
322
324
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helse do
|
323
325
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# Prepare the read.
|
324
|
-
abus_r <= abus_r + 1
|
326
|
+
# abus_r <= abus_r + 1
|
327
|
+
if 2**size.width != size then
|
328
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
329
|
+
else
|
330
|
+
abus_r <= abus_r + 1
|
331
|
+
end
|
325
332
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trig_r <= 1
|
326
333
|
end
|
327
334
|
end
|
@@ -382,7 +389,12 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
382
389
|
end
|
383
390
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helse do
|
384
391
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# Prepare the read.
|
385
|
-
abus_r <= abus_r - 1
|
392
|
+
# abus_r <= abus_r - 1
|
393
|
+
if 2**size.width != size then
|
394
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
395
|
+
else
|
396
|
+
abus_r <= abus_r - 1
|
397
|
+
end
|
386
398
|
trig_r <= 1
|
387
399
|
end
|
388
400
|
end
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@@ -434,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
434
446
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size = size.to_i
|
435
447
|
# Compute the address bus width from the size.
|
436
448
|
awidth = (size-1).width
|
449
|
+
awidth = 1 if awidth == 0
|
437
450
|
# Process the table of reset mapping for the branches.
|
438
451
|
# puts "first br_rsts=#{br_rsts}"
|
439
452
|
# if br_rsts.is_a?(Array) then
|
@@ -593,7 +606,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
593
606
|
end
|
594
607
|
helse do
|
595
608
|
# Prepare the read.
|
596
|
-
abus_r <= abus_r + 1
|
609
|
+
# abus_r <= abus_r + 1
|
610
|
+
if 2**size.width != size then
|
611
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
612
|
+
else
|
613
|
+
abus_r <= abus_r + 1
|
614
|
+
end
|
597
615
|
trig_r <= 1
|
598
616
|
end
|
599
617
|
end
|
@@ -630,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
630
648
|
# No reset, so can perform the write.
|
631
649
|
blk.call if blk
|
632
650
|
# Prepare the write.
|
633
|
-
abus_w <= abus_w + 1
|
651
|
+
# abus_w <= abus_w + 1
|
652
|
+
if 2**size.width != size then
|
653
|
+
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
654
|
+
else
|
655
|
+
abus_w <= abus_w + 1
|
656
|
+
end
|
634
657
|
trig_w <= 1
|
635
658
|
dbus_w <= target
|
636
659
|
end
|
@@ -692,7 +715,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
692
715
|
end
|
693
716
|
helse do
|
694
717
|
# Prepare the read.
|
695
|
-
abus_r <= abus_r - 1
|
718
|
+
# abus_r <= abus_r - 1
|
719
|
+
if 2**size.width != size then
|
720
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
721
|
+
else
|
722
|
+
abus_r <= abus_r - 1
|
723
|
+
end
|
696
724
|
trig_r <= 1
|
697
725
|
end
|
698
726
|
end
|
@@ -729,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
729
757
|
# No reset, so can perform the write.
|
730
758
|
blk.call if blk
|
731
759
|
# Prepare the write.
|
732
|
-
abus_w <= abus_w - 1
|
760
|
+
# abus_w <= abus_w - 1
|
761
|
+
if 2**size.width != size then
|
762
|
+
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
763
|
+
else
|
764
|
+
abus_w <= abus_w - 1
|
765
|
+
end
|
733
766
|
trig_w <= 1
|
734
767
|
dbus_w <= target
|
735
768
|
end
|
@@ -923,6 +956,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
923
956
|
reader_input rst_name
|
924
957
|
end
|
925
958
|
# Declares the address counter.
|
959
|
+
awidth = size.width-1
|
960
|
+
awidth = 1 if awidth == 0
|
926
961
|
[size.width-1].inner :abus_r
|
927
962
|
reader_inout :abus_r
|
928
963
|
|
@@ -946,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
946
981
|
end
|
947
982
|
blk.call if blk
|
948
983
|
# Prepare the next read.
|
949
|
-
abus_r <= abus_r + 1
|
984
|
+
# abus_r <= abus_r + 1
|
985
|
+
if 2**size.width != size then
|
986
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
987
|
+
else
|
988
|
+
abus_r <= abus_r + 1
|
989
|
+
end
|
950
990
|
end
|
951
991
|
end
|
952
992
|
end
|
@@ -985,7 +1025,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
985
1025
|
end
|
986
1026
|
blk.call if blk
|
987
1027
|
# Prepare the next write.
|
988
|
-
abus_w <= abus_w + 1
|
1028
|
+
# abus_w <= abus_w + 1
|
1029
|
+
if 2**size.width != size then
|
1030
|
+
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
1031
|
+
else
|
1032
|
+
abus_w <= abus_w + 1
|
1033
|
+
end
|
989
1034
|
end
|
990
1035
|
end
|
991
1036
|
end
|
@@ -1003,6 +1048,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1003
1048
|
reader_input rst_name
|
1004
1049
|
end
|
1005
1050
|
# Declares the address counter.
|
1051
|
+
awidth = size.width - 1
|
1052
|
+
awidth = 1 if awidth == 0
|
1006
1053
|
[size.width-1].inner :abus_r
|
1007
1054
|
reader_inout :abus_r
|
1008
1055
|
|
@@ -1026,7 +1073,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1026
1073
|
end
|
1027
1074
|
blk.call if blk
|
1028
1075
|
# Prepare the next read.
|
1029
|
-
abus_r <= abus_r - 1
|
1076
|
+
# abus_r <= abus_r - 1
|
1077
|
+
if 2**size.width != size then
|
1078
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
1079
|
+
else
|
1080
|
+
abus_r <= abus_r - 1
|
1081
|
+
end
|
1030
1082
|
end
|
1031
1083
|
end
|
1032
1084
|
end
|
@@ -1065,7 +1117,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1065
1117
|
end
|
1066
1118
|
blk.call if blk
|
1067
1119
|
# Prepare the next write.
|
1068
|
-
abus_w <= abus_w - 1
|
1120
|
+
# abus_w <= abus_w - 1
|
1121
|
+
if 2**size.width != size then
|
1122
|
+
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
1123
|
+
else
|
1124
|
+
abus_w <= abus_w - 1
|
1125
|
+
end
|
1069
1126
|
end
|
1070
1127
|
end
|
1071
1128
|
end
|
@@ -1113,7 +1170,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1113
1170
|
size = size.to_i
|
1114
1171
|
# Compute the address bus width from the size.
|
1115
1172
|
awidth = (size*nbanks-1).width
|
1173
|
+
awidth = 1 if awidth == 0
|
1116
1174
|
awidth_b = (size-1).width # Bank width
|
1175
|
+
awidth_b = 1 if awidth_b == 0
|
1117
1176
|
# Ensures br_srts is a hash.
|
1118
1177
|
br_rsts = br_rsts.to_hash
|
1119
1178
|
|
@@ -1274,7 +1333,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1274
1333
|
blk.call if blk
|
1275
1334
|
end
|
1276
1335
|
# Prepare the read.
|
1277
|
-
abus_r <= abus_r + 1
|
1336
|
+
# abus_r <= abus_r + 1
|
1337
|
+
if 2**size.width != size then
|
1338
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
1339
|
+
else
|
1340
|
+
abus_r <= abus_r + 1
|
1341
|
+
end
|
1278
1342
|
trig_r <= 1
|
1279
1343
|
end
|
1280
1344
|
end
|
@@ -1310,7 +1374,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1310
1374
|
# No reset, so can perform the write.
|
1311
1375
|
blk.call if blk
|
1312
1376
|
# Prepare the write.
|
1313
|
-
abus_w <= abus_w + 1
|
1377
|
+
# abus_w <= abus_w + 1
|
1378
|
+
if 2**size.width != size then
|
1379
|
+
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
1380
|
+
else
|
1381
|
+
abus_w <= abus_w + 1
|
1382
|
+
end
|
1314
1383
|
trig_w <= 1
|
1315
1384
|
dbus_w <= target
|
1316
1385
|
end
|
@@ -1351,7 +1420,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1351
1420
|
blk.call if blk
|
1352
1421
|
end
|
1353
1422
|
# Prepare the read.
|
1354
|
-
abus_r <= abus_r - 1
|
1423
|
+
# abus_r <= abus_r - 1
|
1424
|
+
if 2**size.width != size then
|
1425
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
1426
|
+
else
|
1427
|
+
abus_r <= abus_r - 1
|
1428
|
+
end
|
1355
1429
|
trig_r <= 1
|
1356
1430
|
end
|
1357
1431
|
end
|
@@ -1388,6 +1462,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1388
1462
|
blk.call if blk
|
1389
1463
|
# Prepare the write.
|
1390
1464
|
abus_w <= abus_w - 1
|
1465
|
+
if 2**size.width != size then
|
1466
|
+
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
1467
|
+
else
|
1468
|
+
abus_w <= abus_w - 1
|
1469
|
+
end
|
1391
1470
|
trig_w <= 1
|
1392
1471
|
dbus_w <= target
|
1393
1472
|
end
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.4.
|
4
|
+
version: 2.4.10
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2020-10-
|
11
|
+
date: 2020-10-16 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -125,6 +125,7 @@ files:
|
|
125
125
|
- lib/HDLRuby/hdr_samples/with_linear.rb
|
126
126
|
- lib/HDLRuby/hdr_samples/with_loop.rb
|
127
127
|
- lib/HDLRuby/hdr_samples/with_memory.rb
|
128
|
+
- lib/HDLRuby/hdr_samples/with_memory_rom.rb
|
128
129
|
- lib/HDLRuby/hdr_samples/with_multi_channels.rb
|
129
130
|
- lib/HDLRuby/hdr_samples/with_reconf.rb
|
130
131
|
- lib/HDLRuby/hdrcc.rb
|