HDLRuby 2.2.8 → 2.2.9
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- checksums.yaml +4 -4
- data/lib/HDLRuby/high_samples/values.rb +3 -0
- data/lib/HDLRuby/hruby_high.rb +5 -3
- data/lib/HDLRuby/hruby_types.rb +11 -0
- data/lib/HDLRuby/hruby_verilog.rb +2 -0
- data/lib/HDLRuby/std/channel.rb +25 -0
- data/lib/HDLRuby/std/memory.rb +236 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 19ade67ae4d1c2ae0cf6c1a5ba8bce4fb82d7026e9e902eb106401ab7c83ab82
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4
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data.tar.gz: b112f3450d5846324538438ddfae966cabdcb651cf5a0d90c3dfca5f65b1030c
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5
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SHA512:
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6
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metadata.gz:
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7
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data.tar.gz:
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6
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+
metadata.gz: 455b3d833372e5620ec3ba90bdc9d4b418e315a21cc61aeec3ccfe60e69ca55db152679b564c6c5568787205646541a476fe07c4ced066a977d22263a7e9ef8c
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7
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+
data.tar.gz: 8bb1ea95785e99a3091db489f899acecd903512d6a28a0e6eaccea7b163265fcdd6e07708c1e06a8688c4172e9abe0c67bdf08281f7719ea3bd5f478cca866e6
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data/lib/HDLRuby/hruby_high.rb
CHANGED
@@ -2403,12 +2403,14 @@ module HDLRuby::High
|
|
2403
2403
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|
2404
2404
|
# Left rotate of +n+ bits.
|
2405
2405
|
def lr(n)
|
2406
|
-
|
2406
|
+
w = self.type.width
|
2407
|
+
return [self[w-(n+1)..0], self[w-1..w-(n)]]
|
2407
2408
|
end
|
2408
2409
|
|
2409
2410
|
# Right rotate of +n+ bits.
|
2410
2411
|
def rr(n)
|
2411
|
-
|
2412
|
+
w = self.type.width
|
2413
|
+
return [self[(n-1)..0], self[w-1..n]]
|
2412
2414
|
end
|
2413
2415
|
|
2414
2416
|
# Coerce by forcing convertion of obj to expression.
|
@@ -2427,7 +2429,7 @@ module HDLRuby::High
|
|
2427
2429
|
# Adds the binary operations generation.
|
2428
2430
|
[:"+",:"-",:"*",:"/",:"%",:"**",
|
2429
2431
|
:"&",:"|",:"^",
|
2430
|
-
:"<<",:">>"
|
2432
|
+
:"<<",:">>",# :ls,:rs,:lr,:rr, # ls, rs lr and rr are treated separately
|
2431
2433
|
:"==",:"!=",:"<",:">",:"<=",:">="].each do |operator|
|
2432
2434
|
meth = proc do |right|
|
2433
2435
|
expr = self.to_expr
|
data/lib/HDLRuby/hruby_types.rb
CHANGED
@@ -226,8 +226,19 @@ module HDLRuby
|
|
226
226
|
end
|
227
227
|
end
|
228
228
|
|
229
|
+
alias_method :ls, :<<
|
230
|
+
|
229
231
|
# Shift right
|
230
232
|
alias_method :>>, :<<
|
233
|
+
alias_method :rs, :<<
|
234
|
+
|
235
|
+
# Rotate left.
|
236
|
+
def lr(type)
|
237
|
+
return self
|
238
|
+
end
|
239
|
+
|
240
|
+
# Rotate right.
|
241
|
+
alias_method :rr, :lr
|
231
242
|
|
232
243
|
|
233
244
|
end
|
data/lib/HDLRuby/std/channel.rb
CHANGED
@@ -820,5 +820,30 @@ module HDLRuby::High::Std
|
|
820
820
|
end
|
821
821
|
end
|
822
822
|
|
823
|
+
|
823
824
|
end
|
824
825
|
|
826
|
+
|
827
|
+
module HDLRuby::High
|
828
|
+
|
829
|
+
## Enhance expressions with possibility to act like a reading branch.
|
830
|
+
module HExpression
|
831
|
+
## Transmits the expression to +target+ and execute +ruby_block+ if
|
832
|
+
# any.
|
833
|
+
def read(target,&ruby_block)
|
834
|
+
target <= self
|
835
|
+
ruby_block.call if ruby_block
|
836
|
+
end
|
837
|
+
end
|
838
|
+
|
839
|
+
|
840
|
+
## Enhance references with possibility to act like a writing branch.
|
841
|
+
module HRef
|
842
|
+
## Transmits +target+ to the reference and execute +ruby_block+ if
|
843
|
+
# any.
|
844
|
+
def write(target,&ruby_block)
|
845
|
+
self <= target
|
846
|
+
ruby_block.call if ruby_block
|
847
|
+
end
|
848
|
+
end
|
849
|
+
end
|
data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -407,3 +407,239 @@ end
|
|
407
407
|
|
408
408
|
|
409
409
|
|
410
|
+
# Register file supporting multiple parallel accesses with distinct read and
|
411
|
+
# write ports of +size+ elements of +typ+ typ, syncrhonized on +clk+
|
412
|
+
# and reset on +rst+.
|
413
|
+
# At each rising edge of +clk+ a read and a write is guaranteed to be
|
414
|
+
# completed provided they are triggered.
|
415
|
+
# +br_rsts+ are reset names on the branches, if not given, a reset input
|
416
|
+
# is added and connected to rst.
|
417
|
+
#
|
418
|
+
# NOTE:
|
419
|
+
#
|
420
|
+
# * such memories uses the following arrayes of ports:
|
421
|
+
# - dbus_rs: read data buses (inputs)
|
422
|
+
# - dbus_ws: write data buses (outputs)
|
423
|
+
#
|
424
|
+
# * The following branches are possible (only one read and one write can
|
425
|
+
# be used per channel)
|
426
|
+
# - rnum: read by register number, the number must be a defined value.
|
427
|
+
# - wnum: writer by register number, the number must be a defined value.
|
428
|
+
# - raddr: read by address
|
429
|
+
# - waddr: read by address
|
430
|
+
# - rinc: read by automatically incremented address.
|
431
|
+
# - winc: write by automatically incremented address.
|
432
|
+
# - rdec: read by automatically decremented address.
|
433
|
+
# - wdec: write by automatically decremented address.
|
434
|
+
# - rque: read in queue mode: automatically incremented address ensuring
|
435
|
+
# the read address is always different from the write address.
|
436
|
+
# - wque: write in queue mode: automatically incremented address ensuring
|
437
|
+
# the write address is always differnet from the read address.
|
438
|
+
#
|
439
|
+
HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
440
|
+
# Ensure typ is a type.
|
441
|
+
typ = typ.to_type
|
442
|
+
# Ensure size in an integer.
|
443
|
+
size = size.to_i
|
444
|
+
# Process the table of reset mapping for the branches.
|
445
|
+
# puts "first br_rsts=#{br_rsts}"
|
446
|
+
if br_rsts.is_a?(Array) then
|
447
|
+
# It is a list, convert it to a hash with the following order:
|
448
|
+
# raddr, waddr, rinc, winc, rdec, wdec, rque, wque
|
449
|
+
# If there is only two entries they will be duplicated and mapped
|
450
|
+
# as follows:
|
451
|
+
# [raddr,waddr], [rinc,winc], [rdec,wdec], [rque,wque]
|
452
|
+
# If there is only one entry it will be duplicated and mapped as
|
453
|
+
# follows:
|
454
|
+
# raddr, rinc, rdec, rque
|
455
|
+
if br_rsts.size == 2 then
|
456
|
+
br_rsts = br_rsts * 4
|
457
|
+
elsif br_rsts.size == 1 then
|
458
|
+
br_rsts = br_rsts * 8
|
459
|
+
end
|
460
|
+
br_rsts = { raddr: br_rsts[0], waddr: br_rsts[1],
|
461
|
+
rinc: br_rsts[2], winc: br_rsts[3],
|
462
|
+
rdec: br_rsts[4], wdec: br_rsts[5],
|
463
|
+
rque: br_rsts[6], wque: br_rsts[6] }
|
464
|
+
end
|
465
|
+
unless br_rsts.respond_to?(:[])
|
466
|
+
raise "Invalid reset mapping description: #{br_rsts}"
|
467
|
+
end
|
468
|
+
|
469
|
+
# Declare the registers.
|
470
|
+
size.times do |i|
|
471
|
+
typ.inner :"reg_#{i}"
|
472
|
+
end
|
473
|
+
|
474
|
+
# Defines the ports of the memory as branchs of the channel.
|
475
|
+
|
476
|
+
# The number branch (accesser).
|
477
|
+
brancher(:anum) do
|
478
|
+
size.times { |i| accesser_inout :"reg_#{i}" }
|
479
|
+
|
480
|
+
# Defines the read procedure of register number +num+
|
481
|
+
# using +target+ as target of access result.
|
482
|
+
reader do |blk,num,target|
|
483
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
484
|
+
# The read procedure.
|
485
|
+
par do
|
486
|
+
# No reset, so can perform the read.
|
487
|
+
target <= regs[num]
|
488
|
+
blk.call if blk
|
489
|
+
end
|
490
|
+
end
|
491
|
+
|
492
|
+
# Defines the read procedure of register number +num+
|
493
|
+
# using +target+ as target of access result.
|
494
|
+
writer do |blk,num,target|
|
495
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
496
|
+
# The write procedure.
|
497
|
+
par do
|
498
|
+
regs[num] <= target
|
499
|
+
blk.call if blk
|
500
|
+
end
|
501
|
+
end
|
502
|
+
end
|
503
|
+
|
504
|
+
|
505
|
+
# The address branches.
|
506
|
+
# Read with address
|
507
|
+
brancher(:raddr) do
|
508
|
+
size.times { |i| reader_input :"reg_#{i}" }
|
509
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
510
|
+
if br_rsts[:raddr] then
|
511
|
+
rst_name = br_rsts[:raddr].to_sym
|
512
|
+
else
|
513
|
+
rst_name = rst.name
|
514
|
+
reader_input rst_name
|
515
|
+
end
|
516
|
+
|
517
|
+
# Defines the read procedure at address +addr+
|
518
|
+
# using +target+ as target of access result.
|
519
|
+
reader do |blk,addr,target|
|
520
|
+
# The read procedure.
|
521
|
+
rst = send(rst_name)
|
522
|
+
par do
|
523
|
+
hif(rst == 0) do
|
524
|
+
# No reset, so can perform the read.
|
525
|
+
hcase(addr)
|
526
|
+
size.times do |i|
|
527
|
+
hwhen(i) { target <= regs[i] }
|
528
|
+
end
|
529
|
+
blk.call if blk
|
530
|
+
end
|
531
|
+
end
|
532
|
+
end
|
533
|
+
end
|
534
|
+
|
535
|
+
# Write with address
|
536
|
+
brancher(:waddr) do
|
537
|
+
size.times { |i| writer_output :"reg_#{i}" }
|
538
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
539
|
+
if br_rsts[:waddr] then
|
540
|
+
rst_name = br_rsts[:waddr].to_sym
|
541
|
+
else
|
542
|
+
rst_name = rst.name
|
543
|
+
writer_input rst_name
|
544
|
+
end
|
545
|
+
|
546
|
+
# Defines the writer procedure at address +addr+
|
547
|
+
# using +target+ as target of access.
|
548
|
+
writer do |blk,addr,target|
|
549
|
+
# The writer procedure.
|
550
|
+
rst = send(rst_name)
|
551
|
+
par do
|
552
|
+
hif(rst == 0) do
|
553
|
+
# No reset, so can perform the read.
|
554
|
+
hcase(addr)
|
555
|
+
size.times do |i|
|
556
|
+
hwhen(i) { regs[i] <= target }
|
557
|
+
end
|
558
|
+
blk.call if blk
|
559
|
+
end
|
560
|
+
end
|
561
|
+
end
|
562
|
+
end
|
563
|
+
|
564
|
+
|
565
|
+
# The increment branches.
|
566
|
+
# Read with increment
|
567
|
+
brancher(:rinc) do
|
568
|
+
size.times { |i| reader_input :"reg_#{i}" }
|
569
|
+
if br_rsts[:rinc] then
|
570
|
+
rst_name = br_rsts[:rinc].to_sym
|
571
|
+
else
|
572
|
+
rst_name = rst.name
|
573
|
+
reader_input rst_name
|
574
|
+
end
|
575
|
+
# Declares the address counter.
|
576
|
+
[size.width-1].inner :abus_r
|
577
|
+
reader_inout :abus_r
|
578
|
+
|
579
|
+
# Defines the read procedure at address +addr+
|
580
|
+
# using +target+ as target of access result.
|
581
|
+
reader do |blk,target|
|
582
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
583
|
+
# By default the read trigger is 0.
|
584
|
+
rst = send(rst_name)
|
585
|
+
top_block.unshift do
|
586
|
+
# Initialize the address so that the next access is at address 0.
|
587
|
+
hif(rst==1) { abus_r <= 0 }
|
588
|
+
end
|
589
|
+
# The read procedure.
|
590
|
+
par do
|
591
|
+
hif(rst == 0) do
|
592
|
+
# No reset, so can perform the read.
|
593
|
+
hcase(abus_r)
|
594
|
+
size.times do |i|
|
595
|
+
hwhen(i) { target <= regs[i] }
|
596
|
+
end
|
597
|
+
blk.call if blk
|
598
|
+
# Prepare the next read.
|
599
|
+
abus_r <= abus_r + 1
|
600
|
+
end
|
601
|
+
end
|
602
|
+
end
|
603
|
+
end
|
604
|
+
|
605
|
+
# Write with increment
|
606
|
+
brancher(:winc) do
|
607
|
+
size.times { |i| writer_output :"reg_#{i}" }
|
608
|
+
if br_rsts[:winc] then
|
609
|
+
rst_name = br_rsts[:winc].to_sym
|
610
|
+
else
|
611
|
+
rst_name = rst.name
|
612
|
+
reader_input rst_name
|
613
|
+
end
|
614
|
+
# Declares the address counter.
|
615
|
+
[size.width-1].inner :abus_w
|
616
|
+
reader_inout :abus_w
|
617
|
+
|
618
|
+
# Defines the write procedure at address +addr+
|
619
|
+
# using +target+ as target of access result.
|
620
|
+
writer do |blk,target|
|
621
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
622
|
+
# By default the read trigger is 0.
|
623
|
+
rst = send(rst_name)
|
624
|
+
top_block.unshift do
|
625
|
+
# Initialize the address so that the next access is at address 0.
|
626
|
+
hif(rst==1) { abus_w <= 0 }
|
627
|
+
end
|
628
|
+
# The read procedure.
|
629
|
+
par do
|
630
|
+
hif(rst == 0) do
|
631
|
+
# No reset, so can perform the read.
|
632
|
+
hcase(abus_w)
|
633
|
+
size.times do |i|
|
634
|
+
hwhen(i) { regs[i] <= target }
|
635
|
+
end
|
636
|
+
blk.call if blk
|
637
|
+
# Prepare the next write.
|
638
|
+
abus_w <= abus_w + 1
|
639
|
+
end
|
640
|
+
end
|
641
|
+
end
|
642
|
+
end
|
643
|
+
|
644
|
+
|
645
|
+
end
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.2.
|
4
|
+
version: 2.2.9
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2020-03-
|
11
|
+
date: 2020-03-17 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|