HDLRuby 2.2.9 → 2.2.10

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hdr_samples/rom.rb

@@ -1,10 +1,14 @@
 
 # Describes an 8-bit data 4-bit address ROM.
 system :rom4_8 do
-    [3..0].input :addr
-    [7..0].output :data
+    [2..0].input :addr
+    [7..0].output :data0,:data1,:data2
 
-    bit[7..0][2**4].constant content: (2**4).times.to_a
+    bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
+    bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
+    bit[7..0][-8].constant content2: (8).times.to_a
 
-    data <= content[addr]
+    data0 <= content0[addr]
+    data1 <= content1[addr]
+    data2 <= content2[addr]
 end

data/lib/HDLRuby/hdrcc.rb

@@ -576,6 +576,7 @@ elsif $options[:verilog] then
         systemT.to_global_systemTs!
         # systemT.break_types!
         # systemT.expand_types!
+        systemT.initial_concat_to_timed!
         systemT.with_port!
     end
     # # Verilog generation

data/lib/HDLRuby/hruby_low_mutable.rb

@@ -463,14 +463,14 @@ module HDLRuby::Low
             end
         end
 
-        # Sets the value.
+        # Sets the value (can also be nil for removing the value).
         def set_value!(value)
             # Check and set teh value.
-            unless value.is_a?(Expression) then
-                raise AnyError, "Invalid class for a constant: #{val.class}"
+            unless value == nil || value.is_a?(Expression) then
+                raise AnyError, "Invalid class for a constant: #{value.class}"
             end
             @value = value
-            value.parent = self
+            value.parent = self unless value == nil
         end
 
     end

data/lib/HDLRuby/hruby_low_without_concat.rb

@@ -22,6 +22,15 @@ module HDLRuby::Low
             self.scope.break_concat_assigns!
         end
 
+        # Converts initial concat of values of signals to assignment in
+        # timed blocks (for making the code compatible with verilog
+        # translation).
+        #
+        # NOTE: Assumes such array as at the top level.
+        def initial_concat_to_timed!
+            self.scope.initial_concat_to_timed!
+        end
+
     end
 
     ## Extends the Scope class with functionality for breaking assingments
@@ -47,6 +56,48 @@ module HDLRuby::Low
                 end
             end
         end
+
+        # Converts initial array of value of signals to assignment in
+        # timed blocks (for making the code compatible with verilog
+        # translation).
+        #
+        # NOTE: Assumes such array as at the top level.
+        def initial_concat_to_timed!
+            # Gather the signal with concat as initial values.
+            sigs = []
+            # For the interface signals of the upper system.
+            self.parent.each_signal do |sig|
+                sigs << sig if sig.value.is_a?(Concat)
+            end
+            # For the inner signals of the scope.
+            self.each_signal do |sig|
+                sigs << sig if sig.value.is_a?(Concat)
+            end
+            # No initial concat? End here.
+            return if sigs.empty?
+            
+            # Create a timed block for moving the concat initialization
+            # to it.
+            initial = TimeBlock.new(:seq)
+            self.add_behavior(TimeBehavior.new(initial))
+            # Adds to it the initializations.
+            sigs.each do |sig|
+                name = sig.name
+                styp = sig.type
+                btyp = styp.base
+                value = sig.value
+                sig.value.each_expression.with_index do |expr,i|
+                    left = RefIndex.new(btyp,
+                                        RefName.new(styp,RefThis.new,name),
+                                        i.to_expr)
+                    initial.add_statement(Transmit.new(left,expr.clone))
+                end
+            end
+            # Remove the initial values from the signals.
+            sigs.each do |sig|
+                sig.set_value!(nil)
+            end
+        end
     end
 
     ## Extends the Block class with functionality for breaking assingments

data/lib/HDLRuby/hruby_low_without_namespace.rb

@@ -317,7 +317,7 @@ module HDLRuby::Low
                 # And create a new type from current type.
                 # Maybe the new type already exists.
                 ndef = types[self]
-                return self if ndef # Yes, already exists.
+                return ndef if ndef # Yes, already exists.
                 # No, create and register a new typedef.
                 ndef = TypeDef.new(HDLRuby.uniq_name,self)
                 types[self] = ndef

data/lib/HDLRuby/hruby_verilog.rb

@@ -1501,6 +1501,9 @@ class Case
                 whens.statement.each_statement do |statement|
                     result << "#{statement.to_verilog}"
                 end
+            else
+                # Empty statement case.
+                result << "\n"
             end
         end
         # The default part is stored in default instead of when. Reads and processes in the same way as when.
@@ -1737,6 +1740,13 @@ class SystemT
         self.each_inner do |inner|
             regs << inner.to_verilog if inner.value
         end
+        # And the array types signals.
+        self.each_signal do |sig|
+            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+        end
+        self.each_inner do |sig|
+            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+        end
 
         # Code generation
         inputs = 0
@@ -1851,7 +1861,6 @@ class SystemT
 
         # Declare "inner".
         self.each_inner do |inner|
-            # puts "for inner: #{inner.to_verilog}"
             # if regs.include?(inner.name) then
             if regs.include?(inner.to_verilog) then
                 code << "   reg"

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.2.9"
+  VERSION = "2.2.10"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.2.9
+  version: 2.2.10
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-03-17 00:00:00.000000000 Z
+date: 2020-03-18 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler