HDLRuby 2.1.2 → 2.1.5

checksums.yaml

@@ -1,7 +1,7 @@
 ---
-SHA1:
-  metadata.gz: 184d23d99443c8b8dbfe750f4cbfc05322be054f
-  data.tar.gz: 54030243baadbc7999a265122edac715c17f8f9b
+SHA256:
+  metadata.gz: c4b9674ac3417d63639cd42264b6e5587a64a4fb801587adf864e8617a118931
+  data.tar.gz: 1800e2649fd77e1e7e34f44bd5357e9425c35ba9771fad8f946bc992a6cb59e3
 SHA512:
-  metadata.gz: 3bd71ebfa372f55deef0a675b64a8de523e3b12bf56a8e67a1c111de0136821c69a835b6ddf91d294e9ad145f89a3a9caa639b2bcddae2278d64b6607eeaba1b
-  data.tar.gz: aa617a1cf9ea4054644e484dff24b00cab51e5f3f618c9140abfd53fb682dfafd468bbd81734364e3961c9dc4b22de7c6b5e6ecd060cde15ca6d6790e6b3d5e0
+  metadata.gz: 485fb494e96a3a1dcabbd9dcf6a70c4ca8a6ba3dd84dd3229450a0f3165aa27583f43bc8c07bfe61df98441426c0b66b703a8c2057f9948fb9b82bbfebbb9eb6
+  data.tar.gz: 39ec1e3ff2b4a24b6a4adf8403738d31de1a0009e48c043d276ee5f3db3cb840d82da1c37eb208f4bb214b2c008e9b264983c1b750704b8646d6b6f25fea3894

data/HDLRuby.gemspec

@@ -28,7 +28,9 @@ Gem::Specification.new do |spec|
   spec.require_paths = ["lib","lib/HDLRuby"]
 
   spec.required_ruby_version = '>= 2.0'
-  spec.add_development_dependency "bundler", "~> 2.0.1"
-  spec.add_development_dependency "rake", "~> 10.0"
+  # spec.add_development_dependency "bundler", "~> 2.0.1"
+  # spec.add_development_dependency "rake", "~> 10.0"
+  spec.add_development_dependency "bundler", ">= 2.0.1"
+  spec.add_development_dependency "rake", ">= 10.0"
   # spec.add_development_dependency "minitest", "~> 5.0"
 end

data/README.md

@@ -54,6 +54,7 @@ Where:
 | `-D, --debug`     | Set the HDLRuby debug mode |
 | `-t, --top system`| Specify the top system describing the circuit to compile |
 | `-p, --param x,y,z`     | Specify the generic parameters                 |
+| `--version `      | Print the version number, then exit                  |
 | `-h, --help`      | Show the help message                                    |
 
 __Notes__:
@@ -1059,8 +1060,11 @@ __Note__:
     ```
   - Parallel mode can be set the same way using `par`.
 
-Finally, it often happens that a behavior contains only one statement.
-In such a case, the description can be shortened using the `at` operator as follows:
+### Extra features for the description of behaviors
+
+#### Single-statement behaviors
+
+It often happens that a behavior contains only one statement.  In such a case, the description can be shortened using the `at` operator as follows:
 
 ```ruby
 ( statement ).at(<list of events>)
@@ -1087,6 +1091,41 @@ For sake of consistency, this operator can also be applied on block statements a
   end ).at(clk.posedge)
 ```
 
+#### Insertion of statements at the beginning of a block
+
+By default, the statements of a  block are added in order of appearance in the code. However, it is also possible to insert statements at the top of the current block using the unshift command within a block as follows:
+
+```ruby
+unshift do
+   <list of statements>
+end
+```
+
+For example the following code inserts two statements at the beginning of the current block:
+
+```ruby
+par do
+   x <= y + z
+   unshift do
+      a <= b - c
+      u <= v & w
+    end
+end
+```
+
+The code above will actually result in the following block:
+
+```ruby
+par do
+   a <= b - c
+   u <= v & w
+   x <= y + z
+end
+```
+
+__Note__: 
+ - While of no practical use for simple circuit description, this feature can be used in advanced generic component descriptions.
+
 
 ## Events
 <a name="events"></a>
@@ -1568,11 +1607,11 @@ The type puns include `to_bit`, `to_unsigned` and `to_signed` that convert expre
 
 ```ruby
 [ up: signed[3..0], down: unsigned[3..0] ].inner :sig
-sig.to_bit <= b01010011
+sig.to_bit <= _b01010011
 ```
 
 The type casts change both the type and the value and are used to adjust the width of the types.  They can only be applied to vectors of `bit`, `signed` or `unsinged` and can only increase the bit width (bit width can be truncated using the selection operator, please refer to the [next section](#concat)).
-These operators comprise the bit width conversions: `ljust`, `rjust`, `zext` and `sext`; they also comprise the bit endianness conversions: `to_big`, `to_little` and `reverse`.
+These operators comprise the bit width conversions: `ljust`, `rjust`, `zext` and `sext`.
 
 More precisely, the bit width conversions operate as follows:
 
@@ -1603,14 +1642,6 @@ More precisely, the bit width conversions operate as follows:
    sig1 <= sig0.sext(12)
    ```
 
-Finally, the bit endianness conversions operate as follows:
-
-- `to_big` ensures the type of the converted expression is big endian. If the initial expression is already big endian, it is left as is, otherwise its bits are reversed.
-
-- `to_little` ensures the type of the converted expression is little endian. If the initial expression is already little endian, it is left as is, otherwise its bits are reversed.
-
-- `reverse` always reverses the bit order of the expression.
-
 
 #### Concatenation and selection operators
 <a name="concat"></a>
@@ -1644,7 +1675,7 @@ Concatenation and selection are done using the `[]` operator as follows:
 #### Implicit conversions
 <a name="implicit"></a>
 
-When there is no ambiguity with bit vector types of same endianness, HDLRuby will automatically insert conversion operators when two types are not compatible with one another.  The cases where such implicit conversions are applied are summarized in the following tables where:
+When there is no ambiguity, HDLRuby will automatically insert conversion operators when two types are not compatible with one another.  The cases where such implicit conversions are applied are summarized in the following tables where:
 
  - `operator` is the operator in use
  - `result width` is the width of the result's type
@@ -2268,8 +2299,9 @@ In order to get information about the current state of the hardware description
 | `is_seq?`      | bit            | tells if current parallel block is sequential|
 | `is_clocked?`  | bit            | tells if current behavior is clocked (activated on a sole rising or falling edge of a signal) |
 | `cur_block`    | block          | gets the current block                     |
-| `cur_behavior` | behavior       | gets the current behavior                  |
-| `cur_systemT`  | system         | gets the current system                    |
+| `cur_behavior` | behavior       | gets the current behavior              |
+| `cur_systemT`  | system         | gets the current system                |
+| `top_block  `  | block          | gets the top block of the current behavior |
 | `one_up`       | block/system   | gets the upper construct (block or system) |
 | `last_one`     | any            | last declared construct                    |
 
@@ -2730,15 +2762,21 @@ end
 
 This library provides a unified interface to complex communication protocols through a new kind of components called the channels that abstract the details of communication protocols. The channels can be used similarly to the ports of a system and are used through a unified interface so that changing the kind of channel, i.e., the communication protocol, does not require any modification of the code.
 
+### Using a channel
+
 A channel is used similarly to a pipe: it has an input where data can be written and an output where data can be read. The ordering of the data and the synchronization depend on the internals of the channel, e.g., a channel can be FIFO or LIFO. The interaction with the channel is done using the following methods:
  
- * `output <name>`: generate ports in the system for writing to the channel and associate them to `name`
  * `input <name>`: generate ports in the system for reading from the channel amd associate them to `name`
+ * `output <name>`: generate ports in the system for writing to the channel and associate them to `name`
+ * `inout <name>`: generate ports in the system for reading and writing to the channel and associate them to `name`
+ * `inner <name>`: generates inner signals for accessing directly the channel
+
+__Note__: `input`, `output`, `inout` and `inner` for channels work similarly to the ones of data types for declaring signals. In particular, `input`, `output` and `inout` are to be used in systems that do not include the channel and `inner` is to be used in the system that include the channel.
 
 When the channel ports are declared, they can be accessed using the following methods depending on whether they are writing or reading ports:
 
- * `write(<value>) <block>`: write `value` to the channel and execute `block` when `write` completes. Both `value` and `block` may be omitted depending on the kind of channel.
- * `read(<target>) <block>`: read the channel, assign the result to signal `target` and execute `block` when the read completes. Both `target` and `block` may be omitted depending on the kind of channel.
+ * `write(<args>) <block>`: write to the channel and execute `block` when `write` completes. `args` is a list of arguments required for performing the write that depend on the channel.
+ * `read(<args>) <block>`: read the channel and execute `block` when the read completes. `args` is a list of arguments required for performing the write that depend on the channel.
 
 For example, a system sending successive 8-bit values through a channel can be described as follows:
 
@@ -2763,6 +2801,22 @@ end
 
 __Note__: In the code above, the channel is passed as generic argument of the system.
 
+### Channel branches
+
+Some channel may include several branches, they are accessed by name using the following method:
+ 
+ * `branch(<name>)`: gets branch named `name` from the channel. This name can be actually be any ruby object (e.g., a number) but it will be converted internally to a ruby symbol.
+
+A branch is a full fledge channel and is used identically. For instance the following code get access to branch number 0 of channel `ch`, get its inputs port, read it and put the result in signal `val` on rising edges of signal `clk`:
+
+```ruby
+br = ch.branch(0)
+br.input
+par(clk.posedge) { br.read(val) }
+```
+
+### Declaring a channel
+
 A new channel is declared like using the keyword `channel` as follows:
 
 ```ruby
@@ -2773,19 +2827,24 @@ Where `name` is the name of the channel and `block` is a procedure block describ
 
  * `reader_input <list of names>`: declares the input ports on the reader side. The list must give the names of the inner signals of the channel that can be read using the reader procedure.
  * `reader_output <list of names>`: declares the output ports on the reader side. The list must give the names of the inner signals of the channel that can be written using the reader procedure.
- * `writer_input <list of names>`: declares the inputs on the writer side. The list must give the names of the inner signals of the channel that can be read using the writer procedure.
- * `writer_output <list of names>`: declares the outputs on the writer side. The list must give the names of the inner signals of the channel that can be written using the writer procedure.
- * `command <name> <block>`: declares a new command for the channel.
+ * `reader_inout <list of names>`: declares the inout ports on the reader side. The list must give the names of the inner signals of the channel that can be written using the reader procedure.
+ * `writer_input <list of names>`: declares the input ports on the writer side. The list must give the names of the inner signals of the channel that can be read using the writer procedure.
+ * `writer_output <list of names>`: declares the output ports on the writer side. The list must give the names of the inner signals of the channel that can be written using the writer procedure.
+ * `writer_inout <list of names>`: declares the inout ports on the writer side. The list must give the names of the inner signals of the channel that can be written using the writer procedure.
+ * `accesser_input <list of names>`: declares the input ports on both the reader and writer side. The list must give the names of the inner signals of the channel that can be read using the writer procedure.
+ * `accesser_output <list of names>`: declares the output ports on both the reader and writer side. The list must give the names of the inner signals of the channel that can be written using the writer procedure.
+ * `accesser_inout <list of names>`: declares the inout ports on both the reader and writer side. The list must give the names of the inner signals of the channel that can be written using the writer procedure.
  * `reader <block>`: defines the reader's access procedure.
    This procedure is invoked by method `read` of the channel (please refer to the previous example).
- The block takes the following arguments:
+ The first argument of the block must be the following:
    - `blk`: the block to execute when the read completes.
-   - `target`: the signal where to put the read value.
+ Other arguments can be freely defined, and will be required by the `read` method.
  * `writer < block>`: defines the writer's access procedure.
    This procedure is invoked by method `write` of the channel (please refer to the previous example).
- The block takes the following arguments:
+ The first argument of the block must be the following:
    - `blk`: the block to execute when the write completes.
-   - `target`: the signal that contains the value to write.
+ Other arguments can be freely defined, and will be required by the `write` command.
+ * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possiblity to access the internals of the upper channel.
 
 For example, a channel implemented by a simple register of generic type `typ`, that can be set to 0 using the `reset` command can be described as follows:
 

data/lib/HDLRuby/hdr_samples/mei8.rb

@@ -25,9 +25,9 @@ system :mei8 do |prog_file = "./prog.obj"|
     instance :prog do
         [7..0].input  :addr          # The address bus
         [7..0].output :instr         # The instruction bus
-        bit[7..0][-256].constant content: # The content of the memory
+        bit[7..0][-256].constant mem: # The content of the memory
             File.readlines(prog_file).map {|l| l.split[0].to_i(2)}
-        instr <= content[addr]       # The access procedure
+        instr <= mem[addr]       # The access procedure
     end
 
     # The registers.

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -25,11 +25,11 @@ system :mei8 do |prog_file = "./prog_encrypt.obj"|
     instance :prog do
         [7..0].input  :addr          # The address bus
         [7..0].output :instr         # The instruction bus
-        bit[7..0][-256].constant content: # The content of the memory
+        bit[7..0][-256].constant mem: # The content of the memory
             ( File.readlines(prog_file).map {|l| l.split[0] }.select do |l|
             ["0","1"].include?(l[2])
         end.map {|l| l[2..9] } )
-        instr <= content[addr]       # The access procedure
+        instr <= mem[addr]       # The access procedure
     end
 
     # The registers.

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -20,17 +20,15 @@ channel(:handshaker) do |typ|
     # Sets the writer output ports.
     writer_output :buf, :read_valid, :read_ready
 
-    # Defines the reset command for the channel.
-    command(:reset) do
-        par do
-            # Fully locked reader side.
-            read_valid  <= 0
-            read_ready  <= 0
-            # Fully unlocked writer side.
-            write_valid <= 1
-            write_ready <= 1
-        end
-    end
+    # # Defines the reset command for the channel.
+    # command(:reset) do
+    #     # Fully locked reader side.
+    #     read_valid  <= 0
+    #     read_ready  <= 0
+    #     # Fully unlocked writer side.
+    #     write_valid <= 1
+    #     write_ready <= 1
+    # end
 
     # Defines the reader's access procedure.
     reader do |blk,target|
@@ -106,8 +104,8 @@ system :hs_test do
     # Declares the handshaker
     handshaker([8]).(:hs)
 
-    # Sets the reset.
-    hs.reset.at(rst.posedge)
+    # # Sets the reset.
+    # par(rst.posedge) { hs.reset }
 
     # Instantiate the producer.
     producer8(hs).(:producerI).(clk,rst)

data/lib/HDLRuby/hdr_samples/with_memory.rb

@@ -0,0 +1,123 @@
+require 'std/memory.rb'
+
+include HDLRuby::High::Std
+
+
+
+
+# A system accessing a memory.
+system :periph do |mem|
+    # Inputs of the peripheral: clock and reset.
+    input :clk, :rst
+
+    # Inner 8-bit counter for generating addresses.
+    [8].inner :address
+    # Inner 8-bit counter for generating values.
+    [8].inner :value
+    # The memory port.
+    mem.inout :memP
+
+
+    # The value production process
+    par(clk.posedge) do
+        hif(rst) do
+            address <= 0
+        end
+        memP.read(address,value) do
+            value <= value + 1
+            memP.write(address,value) { address <= address + 1 }
+        end
+    end
+end
+
+# A system producing data and writing it to a memory.
+system :producer do |mem|
+    # Clock and reset.
+    input :clk, :rst
+    # The memory port.
+    mem.output :memP
+
+    # Inner 8-bit counter for generating addresses and values
+    [8].inner :count
+
+    # The value production process.
+    par(clk.posedge) do
+        hif(rst) { count <= 0 }
+        helse do
+            memP.write(count,count) { count <= count + 1 }
+        end
+    end
+end
+
+# A system consuming data from a memory.
+system :consumer do |mem|
+    # Clock and reset.
+    input :clk, :rst
+    # The accumumated consumed data list.
+    [8].output :sum
+    # The memory port.
+    mem.input :memP
+
+    # Inner 8-bit counter for generating addresses and values
+    [8].inner :count
+    # Memory access result.
+    [8].inner :res
+
+    # The value production process.
+    par(clk.posedge) do
+        hif(rst) do
+            count <= 255
+            sum <= 0
+        end
+        helse do
+            memP.read(count,res) do
+                count <= count + 1
+                sum <= sum + res
+            end
+        end
+    end
+end
+
+
+
+# A system testing the memory.
+system :mem_test do
+    input :clk,:rst
+
+    # Declares a dual-port 8-bit data and address synchronous memory
+    # on negative edge of clk.
+    mem_sync(2,[8],256,clk.negedge,rst,[:rst,:rst]).(:memI)
+
+    # Instantiate the producer to access port 1 of the memory.
+    periph(memI.branch(1)).(:periphI).(clk,rst)
+    # periph(memI).(:periphI).(clk,rst)
+    memI.branch(0).inner :mem0
+
+    # Inner 8-bit counter for generating addresses.
+    [8].inner :address
+    # Inner 8-bit counter for generating values.
+    [8].inner :value
+
+    # Access the memory.
+    par(clk.posedge) do
+        hif(rst) do
+            address <= 255; value <= 128
+        end
+        # memI.write(0,address,value) { address <= address - 1 }
+        mem0.write(address,value) { address <= address - 1 }
+    end
+
+
+    [8].inner :sum
+
+    # Declares a dual edge 8-bit data and address memory.
+    mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
+
+    # Instantiate the producer to access port waddr of the memory.
+    producer(memDI.branch(:waddr)).(:producerI).(clk,rst)
+
+    # Instantiate the producer to access port raddr of the memory.
+    consumer(memDI.branch(:raddr)).(:consumerI).(clk,rst,sum)
+
+
+end

data/lib/HDLRuby/hdrcc.rb

@@ -3,7 +3,7 @@
 require 'fileutils'
 require 'HDLRuby'
 require 'HDLRuby/hruby_check.rb'
-require 'ripper'
+# require 'ripper'
 require 'HDLRuby/hruby_low2high'
 require 'HDLRuby/hruby_low2c'
 require 'HDLRuby/hruby_low2vhd'
@@ -25,6 +25,8 @@ require 'HDLRuby/hruby_verilog.rb'
 require 'HDLRuby/backend/hruby_allocator'
 require 'HDLRuby/backend/hruby_c_allocator'
 
+require 'HDLRuby/version.rb'
+
 ##
 # HDLRuby compiler interface program
 #####################################
@@ -250,7 +252,7 @@ $optparse = OptionParser.new do |opts|
     opts.separator "* `<output file>` is the output file"
     opts.separator ""
     opts.separator "Options:"
-
+    
     opts.on("-y", "--yaml", "Output in YAML format") do |y|
         $options[:yaml] = y
     end
@@ -311,7 +313,12 @@ $optparse = OptionParser.new do |opts|
     opts.on("-p", "--param x,y,z", "Specify the generic parameters") do |p|
         $options[:param] = p
     end
-    opts.on_tail("-h", "--help", "Show this message") do
+    opts.on("--version", "Print the version number, then exit") do
+        puts "hdrcc: HDLRuby #{HDLRuby::VERSION} compiler"
+        exit
+    end
+    # opts.on_tail("-h", "--help", "Show this message") do
+    opts.on("-h", "--help", "Show this message") do
         puts opts
         exit
     end
@@ -422,10 +429,10 @@ if $allocate_range then
     $allocate_range = [$allocate_range[0]..$allocate_range[1],
                        $allocate_range[2]].compact
     # Create the allocator.
-    allocator = HDLRuby::Low::Allocator.new(*$allocate_range)
+    $allocator = HDLRuby::Low::Allocator.new(*$allocate_range)
     $non_hdlruby.each do |code|
         # Try the C allocator.
-        code.c_code_allocate(allocator)
+        code.c_code_allocate($allocator)
     end
 end
 # Generates its code.
@@ -449,9 +456,9 @@ elsif $options[:hdr] then
     $output << $top_system.to_high
 elsif $options[:clang] then
     # top_system = $top_instance.to_low.systemT
-    top_system = $top_system
+    # top_system = $top_system
     # Preprocess the HW description for valid C generation.
-    top_system.each_systemT_deep do |systemT|
+    $top_system.each_systemT_deep do |systemT|
         # Converts the connections to behaviors.
         systemT.connections_to_behaviors!
         # Break the RefConcat.
@@ -463,10 +470,10 @@ elsif $options[:clang] then
     if $options[:multiple] then
         # Get the base name of the input file, it will be used for
         # generating the main name of the multiple result files.
-        basename = File.basename($input,File.extname($input))
-        basename = $output + "/" + basename
-        # File name counter.
-        count = 0
+        $basename = File.basename($input,File.extname($input))
+        $basename = $output + "/" + $basename
+        # # File name counter.
+        # $namecount = 0
 
         # # Converts the connections to behaviors (C generation does not
         # # support connections).
@@ -476,11 +483,11 @@ elsif $options[:clang] then
 
         # Multiple files generation mode.
         # Generate the h file.
-        hname = $output + "/hruby_sim_gen.h"
-        hnames = [ File.basename(hname) ]
-        outfile = File.open(hname,"w")
+        $hname = $output + "/hruby_sim_gen.h"
+        $hnames = [ File.basename($hname) ]
+        $outfile = File.open($hname,"w")
         # Adds the generated globals
-        top_system.each_systemT_deep do |systemT|
+        $top_system.each_systemT_deep do |systemT|
             # For the h file.
             # hname = $output + "/" +
             #     HDLRuby::Low::Low2C.c_name(systemT.name) +
@@ -489,7 +496,7 @@ elsif $options[:clang] then
             # # Open the file for current systemT
             # output = File.open(hname,"w")
             # Generate the H code in to.
-            outfile << systemT.to_ch
+            $outfile << systemT.to_ch
             # # Close the file.
             # output.close
             # # Clears the name.
@@ -499,25 +506,25 @@ elsif $options[:clang] then
         $non_hdlruby.each do |code|
             code.each_chunk do |chunk|
                 if chunk.name == :sim then
-                    outfile << "extern " + 
+                    $outfile << "extern " + 
                         HDLRuby::Low::Low2C.prototype(chunk.to_c)
                 end
             end
         end
-        outfile.close
+        $outfile.close
 
         # Prepare the initial name for the main file.
-        name = basename + ".c"
+        $name = $basename + ".c"
         # Generate the code for it.
-        main = File.open(name,"w")
+        $main = File.open($name,"w")
 
         # Generate the code of the main function.
         # HDLRuby start code
-        main << HDLRuby::Low::Low2C.main(top_system,
-                                         top_system.each_systemT_deep.to_a.reverse,hnames)
-        main.close
+        $main << HDLRuby::Low::Low2C.main($top_system,
+                                         $top_system.each_systemT_deep.to_a.reverse,$hnames)
+        $main.close
 
-        top_system.each_systemT_deep do |systemT|
+        $top_system.each_systemT_deep do |systemT|
             # For the c file.
             name = $output + "/" +
                 HDLRuby::Low::Low2C.c_name(systemT.name) +
@@ -525,7 +532,7 @@ elsif $options[:clang] then
             # Open the file for current systemT
             outfile = File.open(name,"w")
             # Generate the C code in to.
-            outfile << systemT.to_c(0,*hnames)
+            outfile << systemT.to_c(0,*$hnames)
             # Close the file.
             outfile.close
             # Clears the name.
@@ -533,7 +540,7 @@ elsif $options[:clang] then
         end
     else
         # Single file generation mode.
-        top_system.each_systemT_deep.reverse_each do |systemT|
+        $top_system.each_systemT_deep.reverse_each do |systemT|
             $output << systemT.to_ch
             $output << systemT.to_c
         end
@@ -545,12 +552,12 @@ elsif $options[:clang] then
         # Simulation mode, compile and exectute.
         # Path of the simulator core files.
         # simdir = File.dirname(__FILE__) + "/sim/"
-        simdir = $hdr_dir + "/sim/"
+        $simdir = $hdr_dir + "/sim/"
         # Generate and execute the simulation commands.
         # Kernel.system("cp -n #{simdir}* #{$output}/; cd #{$output}/ ; make -s ; ./hruby_simulator")
-        Dir.entries(simdir).each do |filename| 
+        Dir.entries($simdir).each do |filename| 
             if !File.directory?(filename) && /\.[ch]$/ === filename then
-                FileUtils.cp(simdir + "/" + filename,$output)
+                FileUtils.cp($simdir + "/" + filename,$output)
             end
         end
         Dir.chdir($output)
@@ -561,9 +568,9 @@ elsif $options[:clang] then
 elsif $options[:verilog] then
     # warn("Verilog HDL output is not available yet... but it will be soon, promise!")
     # top_system = $top_instance.to_low.systemT
-    top_system = $top_system
+    # top_system = $top_system
     # Make description compatible with verilog generation.
-    top_system.each_systemT_deep do |systemT|
+    $top_system.each_systemT_deep do |systemT|
         systemT.to_upper_space!
         systemT.to_global_systemTs!
         systemT.break_types!
@@ -575,28 +582,28 @@ elsif $options[:verilog] then
     if $options[:multiple] then
         # Get the base name of the input file, it will be used for
         # generating the main name of the multiple result files.
-        basename = File.basename($input,File.extname($input))
-        basename = $output + "/" + basename
-        # File name counter.
-        count = 0
+        $basename = File.basename($input,File.extname($input))
+        $basename = $output + "/" + $basename
+        # # File name counter.
+        # $namecount = 0
         # Prepare the initial name for the main file.
-        name = basename + ".v"
+        $name = $basename + ".v"
         # Multiple files generation mode.
-        top_system.each_systemT_deep do |systemT|
+        $top_system.each_systemT_deep do |systemT|
             # Generate the name if necessary.
-            unless name
-                name = $output + "/" +
+            unless $name
+                $name = $output + "/" +
                     HDLRuby::Verilog.name_to_verilog(systemT.name) +
                     ".v"
             end
             # Open the file for current systemT
-            outfile = File.open(name,"w")
-            # Generate the VHDL code in to.
+            outfile = File.open($name,"w")
+            # Generate the Verilog code in to.
             outfile << systemT.to_verilog
             # Close the file.
             outfile.close
             # Clears the name.
-            name = nil
+            $name = nil
         end
     else
         # Single file generation mode.
@@ -606,9 +613,9 @@ elsif $options[:verilog] then
     end
 elsif $options[:vhdl] then
     # top_system = $top_instance.to_low.systemT
-    top_system = $top_system
+    # top_system = $top_system
     # Make description compatible with vhdl generation.
-    top_system.each_systemT_deep do |systemT|
+    $top_system.each_systemT_deep do |systemT|
         systemT.outread2inner!            unless $options[:vhdl08] || $options[:alliance]
         systemT.with_boolean!
         systemT.boolean_in_assign2select! unless $options[:alliance]
@@ -626,32 +633,32 @@ elsif $options[:vhdl] then
     if $options[:multiple] then
         # Get the base name of the input file, it will be used for
         # generating the main name of the multiple result files.
-        basename = File.basename($input,File.extname($input))
-        basename = $output + "/" + basename
-        # File name counter.
-        count = 0
+        $basename = File.basename($input,File.extname($input))
+        $basename = $output + "/" + $basename
+        # # File name counter.
+        # $namecount = 0
         # Prepare the initial name for the main file.
-        name = basename + ".vhd"
+        $name = $basename + ".vhd"
         # Multiple files generation mode.
-        top_system.each_systemT_deep do |systemT|
+        $top_system.each_systemT_deep do |systemT|
             # Generate the name if necessary.
-            unless name
-                name = $output + "/" +
+            unless $name
+                $name = $output + "/" +
                     HDLRuby::Low::Low2VHDL.entity_name(systemT.name) +
                     ".vhd"
             end
             # Open the file for current systemT
-            outfile = File.open(name,"w")
+            outfile = File.open($name,"w")
             # Generate the VHDL code in to.
             outfile << systemT.to_vhdl
             # Close the file.
             outfile.close
             # Clears the name.
-            name = nil
+            $name = nil
         end
     else
         # Single file generation mode.
-        top_system.each_systemT_deep.reverse_each do |systemT|
+        $top_system.each_systemT_deep.reverse_each do |systemT|
             $output << systemT.to_vhdl
         end
     end